From mboxrd@z Thu Jan 1 00:00:00 1970 From: Benjamin Herrenschmidt Date: Tue, 10 Jan 2012 22:49:18 +0000 Subject: Re: [PATCH] virtio-pci: Fix endianness of virtio config Message-Id: <1326235758.23910.75.camel@pasglop> List-Id: References: <1326195311.23910.59.camel@pasglop> <4F0CB585.2000206@codemonkey.ws> <485923AD-E235-4412-9B60-2E0736FB74D1@suse.de> In-Reply-To: <485923AD-E235-4412-9B60-2E0736FB74D1@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: Alexander Graf Cc: Anthony Liguori , "qemu-devel@nongnu.org" , "kvm@vger.kernel.org" , kvm-ppc@vger.kernel.org, David Gibson On Tue, 2012-01-10 at 23:41 +0100, Alexander Graf wrote: > > No. Libhw shouldn't be able to know anything about target endianness. > If a device is as brokenly spec'ed as virtio and is coupled to the > "main CPU endianness", it clearly belongs with the CPU, not into > libhw. Ok, can you guys solve this and tell me what I should do ? :-) Cheers, Ben.