From mboxrd@z Thu Jan 1 00:00:00 1970 From: Alexander Graf Date: Thu, 15 Mar 2012 12:11:21 +0000 Subject: [PATCH 52/56] KVM: PPC: Emulate tw and td instructions Message-Id: <1331813485-14722-53-git-send-email-agraf@suse.de> List-Id: References: <1331813485-14722-1-git-send-email-agraf@suse.de> In-Reply-To: <1331813485-14722-1-git-send-email-agraf@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable To: kvm-ppc@vger.kernel.org Cc: kvm@vger.kernel.org There are 4 conditional trapping instructions: tw, twi, td, tdi. The ones with an i take an immediate comparison, the others compare two registers. All of them arrive in the emulator when the condition to trap was successfully fulfilled. Unfortunately, we were only implementing the i versions so far, so let's also add support for the other two. This fixes kernel booting with recents book3s_32 guest kernels. Reported-by: J=C3=B6rg Sommer Signed-off-by: Alexander Graf --- arch/powerpc/kvm/emulate.c | 14 ++++++++++++++ 1 files changed, 14 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/kvm/emulate.c b/arch/powerpc/kvm/emulate.c index e79a620..afc9154 100644 --- a/arch/powerpc/kvm/emulate.c +++ b/arch/powerpc/kvm/emulate.c @@ -35,7 +35,9 @@ #define OP_TRAP 3 #define OP_TRAP_64 2 =20 +#define OP_31_XOP_TRAP 4 #define OP_31_XOP_LWZX 23 +#define OP_31_XOP_TRAP_64 68 #define OP_31_XOP_LBZX 87 #define OP_31_XOP_STWX 151 #define OP_31_XOP_STBX 215 @@ -169,6 +171,18 @@ int kvmppc_emulate_instruction(struct kvm_run *run, st= ruct kvm_vcpu *vcpu) case 31: switch (get_xop(inst)) { =20 + case OP_31_XOP_TRAP: +#ifdef CONFIG_64BIT + case OP_31_XOP_TRAP_64: +#endif +#ifdef CONFIG_PPC_BOOK3S + kvmppc_core_queue_program(vcpu, SRR1_PROGTRAP); +#else + kvmppc_core_queue_program(vcpu, + vcpu->arch.shared->esr | ESR_PTR); +#endif + advance =3D 0; + break; case OP_31_XOP_LWZX: rt =3D get_rt(inst); emulated =3D kvmppc_handle_load(run, vcpu, rt, 4, 1); --=20 1.6.0.2