From mboxrd@z Thu Jan 1 00:00:00 1970 From: Alexander Graf Date: Thu, 31 Oct 2013 21:18:03 +0000 Subject: [PULL 18/51] KVM: PPC: Book3S PR: Handle PP0 page-protection bit in guest HPTEs Message-Id: <1383254316-11243-19-git-send-email-agraf@suse.de> List-Id: References: <1383254316-11243-1-git-send-email-agraf@suse.de> In-Reply-To: <1383254316-11243-1-git-send-email-agraf@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: "kvm@vger.kernel.org mailing list" Cc: kvm-ppc@vger.kernel.org, Gleb Natapov , Paolo Bonzini , Paul Mackerras From: Paul Mackerras 64-bit POWER processors have a three-bit field for page protection in the hashed page table entry (HPTE). Currently we only interpret the two bits that were present in older versions of the architecture. The only defined combination that has the new bit set is 110, meaning read-only for supervisor and no access for user mode. This adds code to kvmppc_mmu_book3s_64_xlate() to interpret the extra bit appropriately. Signed-off-by: Paul Mackerras Signed-off-by: Alexander Graf --- arch/powerpc/kvm/book3s_64_mmu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/powerpc/kvm/book3s_64_mmu.c b/arch/powerpc/kvm/book3s_64_mmu.c index ffcde01..9e6e112 100644 --- a/arch/powerpc/kvm/book3s_64_mmu.c +++ b/arch/powerpc/kvm/book3s_64_mmu.c @@ -298,6 +298,8 @@ do_second: v = pteg[i]; r = pteg[i+1]; pp = (r & HPTE_R_PP) | key; + if (r & HPTE_R_PP0) + pp |= 8; gpte->eaddr = eaddr; gpte->vpage = kvmppc_mmu_book3s_64_ea_to_vp(vcpu, eaddr, data); @@ -319,6 +321,7 @@ do_second: case 3: case 5: case 7: + case 10: gpte->may_read = true; break; } -- 1.8.1.4