From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paul Mackerras Date: Fri, 06 Sep 2013 03:51:08 +0000 Subject: [RFC PATCH 02/10] KVM: PPC: Book3S HV: Don't set DABR on POWER8 Message-Id: <20130906035108.GO29710@iris.ozlabs.ibm.com> List-Id: References: <20130906034820.GM29710@iris.ozlabs.ibm.com> In-Reply-To: <20130906034820.GM29710@iris.ozlabs.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: Alexander Graf , kvm-ppc@vger.kernel.org, kvm@vger.kernel.org From: Michael Neuling POWER8 doesn't have the DABR and DABRX registers; instead it has new DAWR/DAWRX registers, which will be handled in a later patch. Signed-off-by: Michael Neuling Signed-off-by: Paul Mackerras --- arch/powerpc/kvm/book3s_hv_interrupts.S | 2 ++ arch/powerpc/kvm/book3s_hv_rmhandlers.S | 13 ++++++++++--- 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/kvm/book3s_hv_interrupts.S b/arch/powerpc/kvm/book3s_hv_interrupts.S index 2a85bf6..0be3404 100644 --- a/arch/powerpc/kvm/book3s_hv_interrupts.S +++ b/arch/powerpc/kvm/book3s_hv_interrupts.S @@ -57,9 +57,11 @@ BEGIN_FTR_SECTION std r3, HSTATE_DSCR(r13) END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) +BEGIN_FTR_SECTION /* Save host DABR */ mfspr r3, SPRN_DABR std r3, HSTATE_DABR(r13) +END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) /* Hard-disable interrupts */ mfmsr r10 diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S b/arch/powerpc/kvm/book3s_hv_rmhandlers.S index 0721d2a..d4f6f5f 100644 --- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S +++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S @@ -95,11 +95,13 @@ kvmppc_got_guest: /* Back from guest - restore host state and return to caller */ +BEGIN_FTR_SECTION /* Restore host DABR and DABRX */ ld r5,HSTATE_DABR(r13) li r6,7 mtspr SPRN_DABR,r5 mtspr SPRN_DABRX,r6 +END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) /* Restore SPRG3 */ ld r3,PACA_SPRG3(r13) @@ -423,15 +425,17 @@ kvmppc_hv_entry: std r0, PPC_LR_STKOFF(r1) stdu r1, -112(r1) +BEGIN_FTR_SECTION /* Set partition DABR */ /* Do this before re-enabling PMU to avoid P7 DABR corruption bug */ li r5,3 ld r6,VCPU_DABR(r4) mtspr SPRN_DABRX,r5 mtspr SPRN_DABR,r6 -BEGIN_FTR_SECTION + BEGIN_FTR_SECTION_NESTED(89) isync -END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) + END_FTR_SECTION_NESTED(CPU_FTR_ARCH_206, CPU_FTR_ARCH_206, 89) +END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) /* Load guest PMU registers */ /* R4 is live here (vcpu pointer) */ @@ -1716,6 +1720,9 @@ ignore_hdec: b fast_guest_return _GLOBAL(kvmppc_h_set_dabr) +BEGIN_FTR_SECTION + b 2f +END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) std r4,VCPU_DABR(r3) /* Work around P7 bug where DABR can get corrupted on mtspr */ 1: mtspr SPRN_DABR,r4 @@ -1723,7 +1730,7 @@ _GLOBAL(kvmppc_h_set_dabr) cmpd r4, r5 bne 1b isync - li r3,0 +2: li r3,0 blr _GLOBAL(kvmppc_h_cede) -- 1.8.4.rc3