From: Paul Mackerras <paulus@samba.org>
To: Alexander Graf <agraf@suse.de>
Cc: kvm-ppc@vger.kernel.org, kvm@vger.kernel.org
Subject: Re: [PATCH 6/6] KVM: PPC: Book3S PR: Expose TM registers
Date: Tue, 20 May 2014 09:59:26 +0000 [thread overview]
Message-ID: <20140520095926.GA27597@iris.ozlabs.ibm.com> (raw)
In-Reply-To: <537A0273.1070704@suse.de>
On Mon, May 19, 2014 at 03:09:07PM +0200, Alexander Graf wrote:
>
> On 17.05.14 08:20, Paul Mackerras wrote:
> >On Tue, Apr 29, 2014 at 06:17:42PM +0200, Alexander Graf wrote:
> >>POWER8 introduces transactional memory which brings along a number of new
> >>registers and MSR bits.
> >>
> >>Implementing all of those is a pretty big headache, so for now let's at least
> >>emulate enough to make Linux's context switching code happy.
> >[snip]
> >
> >>- if (!(vcpu->arch.fscr & (1ULL << fac))) {
> >>+ /* We get TM interrupts only when EBB is disabled? Sigh. */
> >This comment doesn't make sense to me. Not every reason code reported
> >in the high bits of FSCR corresponds directly to an enable bit in
> >FSCR. In fact, of the 7 defined reason codes in POWER8, only three
> >correspond to an enable bit...
>
> Is there any documentation on which relate to what?
Yes, Power ISA v2.07 book 3S section 6.2.10 describes the FSCR enable
bits and the interruption cause field. There are 6 cause values
defined, of which 3 correspond to enable bits in the FSCR, and the
other 3 correspond to things enabled/disabled in MMCR0 (usermode PMC
anb BHRB access) or MSR (TM stuff).
Paul.
next prev parent reply other threads:[~2014-05-20 9:59 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-04-29 16:17 [PATCH 0/6] KVM: PPC: Book3S PR: Add POWER8 support Alexander Graf
2014-04-29 16:17 ` [PATCH 1/6] KVM: PPC: Book3S PR: Ignore PMU SPRs Alexander Graf
2014-04-30 22:12 ` Paul Mackerras
2014-05-02 8:35 ` Alexander Graf
2014-05-07 7:09 ` Paul Mackerras
2014-05-08 12:11 ` Alexander Graf
2014-04-29 16:17 ` [PATCH 2/6] KVM: PPC: Book3S PR: Emulate TIR register Alexander Graf
2014-04-30 5:51 ` Michael Neuling
2014-04-30 10:06 ` Alexander Graf
2014-04-29 16:17 ` [PATCH 3/6] KVM: PPC: Book3S PR: Handle Facility interrupt and FSCR Alexander Graf
2014-04-29 16:17 ` [PATCH 4/6] KVM: PPC: Book3S PR: Expose TAR facility to guest Alexander Graf
2014-04-29 16:17 ` [PATCH 5/6] KVM: PPC: Book3S PR: Expose EBB registers Alexander Graf
2014-04-29 16:17 ` [PATCH 6/6] KVM: PPC: Book3S PR: Expose TM registers Alexander Graf
2014-05-17 6:20 ` Paul Mackerras
2014-05-19 13:09 ` Alexander Graf
2014-05-20 9:59 ` Paul Mackerras [this message]
2014-05-20 11:49 ` Alexander Graf
2014-05-04 16:48 ` [PATCH 0/6] KVM: PPC: Book3S PR: Add POWER8 support Aneesh Kumar K.V
2014-05-05 11:18 ` Alexander Graf
2014-05-05 14:50 ` Aneesh Kumar K.V
2014-05-05 14:42 ` Alexander Graf
2014-05-05 14:48 ` Aneesh Kumar K.V
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