From mboxrd@z Thu Jan 1 00:00:00 1970 From: David Gibson Date: Fri, 16 Nov 2018 05:25:34 +0000 Subject: Re: [PATCH kernel v3 11/22] powerpc/pseries/npu: Enable platform support Message-Id: <20181116052534.GD23632@umbus> MIME-Version: 1 Content-Type: multipart/mixed; boundary="/unnNtmY43mpUSKx" List-Id: References: <20181113082823.2440-1-aik@ozlabs.ru> <20181113082823.2440-12-aik@ozlabs.ru> In-Reply-To: <20181113082823.2440-12-aik@ozlabs.ru> To: Alexey Kardashevskiy Cc: Alex Williamson , Jose Ricardo Ziviani , Sam Bobroff , Alistair Popple , linuxppc-dev@lists.ozlabs.org, kvm-ppc@vger.kernel.org, Piotr Jaroszynski , Oliver O'Halloran , Andrew Donnellan , Leonardo Augusto =?iso-8859-1?Q?Guimar=E3es?= Garcia , Reza Arbab --/unnNtmY43mpUSKx Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, Nov 13, 2018 at 07:28:12PM +1100, Alexey Kardashevskiy wrote: > We already changed NPU API for GPUs to not to call OPAL and the remaining > bit is initializing NPU structures. >=20 > This uses a new QEMU capability which marks NPU-enabled vPHBs as > "IBM,npu-vphb" and initializes an NPU structure per vPHB. >=20 > Signed-off-by: Alexey Kardashevskiy > --- > arch/powerpc/platforms/pseries/pci.c | 6 ++++++ > 1 file changed, 6 insertions(+) >=20 > diff --git a/arch/powerpc/platforms/pseries/pci.c b/arch/powerpc/platform= s/pseries/pci.c > index 41d8a4d..a50d5e4 100644 > --- a/arch/powerpc/platforms/pseries/pci.c > +++ b/arch/powerpc/platforms/pseries/pci.c > @@ -29,6 +29,7 @@ > #include > #include > #include > +#include > #include "pseries.h" > =20 > #if 0 > @@ -237,6 +238,8 @@ static void __init pSeries_request_regions(void) > =20 > void __init pSeries_final_fixup(void) > { > + struct pci_controller *hose; > + > pSeries_request_regions(); > =20 > eeh_probe_devices(); > @@ -246,6 +249,9 @@ void __init pSeries_final_fixup(void) > ppc_md.pcibios_sriov_enable =3D pseries_pcibios_sriov_enable; > ppc_md.pcibios_sriov_disable =3D pseries_pcibios_sriov_disable; > #endif > + list_for_each_entry(hose, &hose_list, list_node) > + if (of_device_is_compatible(hose->dn, "IBM,npu-vphb")) > + pnv_npu2_init(hose); I take it from this the NPUs are showing up with a compatible property that lists the normal PHB value as well as IBM,npu-vphb. Since AIUI the NPUs act quite differently from other (real) PHBs this seems bogus. Shouldn't they be probed separately? --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson --/unnNtmY43mpUSKx Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAEBCAAdFiEEdfRlhq5hpmzETofcbDjKyiDZs5IFAlvuVM4ACgkQbDjKyiDZ s5JJtg/+INmzR3Ey0HwKITDY4GtSd/zlYoijdxW9CkLO9x00DOP7p72eNK/Cuyua Pn0U7x3DdhIXrLUD4CpTyZOrcjua9xLLQ/bjrReSbgiunTuMhRD2zyXXR/zN3RaT D1CsOxKVQN+J4QEVGXgaDmgzRs8DzQ5LjQkMlgw+R80GOKbqjNp2B7iTlE+X2EK1 YIgE4ACIv2RLeUQedvYboDkBHT26K3+Q3+jL4mEsZPJTNLZoYUsIrqt8BmwzjfcD drhIaxz4PcFkkoH2pbSkO3ksObr8BX+PBa05p6ALiuMl9/VK9NNnODW6WzuIPGSa Qn8RHDneu1MkTnLBJylGKgmLo8WVLWdSQPTBPuxh1+Ip2Ch/b9L4ecfWPE0v/HuY 6dwsZJr0PoVv1lO3xbDZzPNzY6K3MDUpbYyJYdeN8edGtNs291AYri/5n6/rAgjS etlwxR8nlKwWchigLZuxLKfpQN7mh1RVZOaoxwYDRJ1QqNoMnvPOfL9maUxzSPrw dqeXRZLYGR5vfsX+nmGDINuzhMNa0kBBbeaLGVsc5Apm81kvFUDxCvZu8FHdD+g8 /oMm1xAWzZmqkVb0TuH8Obv5/dX6rvKuAtow4h5vY4S/GdWUDGRVBlQfRjLDaEiY F2fn/ZNY58sqi1eaaLEp5CVEBqzyMLxsfZZtKD+8XDCASi321LY= =iuiF -----END PGP SIGNATURE----- --/unnNtmY43mpUSKx--