From mboxrd@z Thu Jan  1 00:00:00 1970
From: Paul Mackerras <paulus@ozlabs.org>
Date: Sun, 17 Feb 2019 23:06:40 +0000
Subject: Re: [PATCH v6] powerpc/64s: reimplement book3s idle code in C
Message-Id: <20190217230640.GA922@blackberry>
List-Id: <kvm-ppc.vger.kernel.org>
References: <20181013120409.1993-1-npiggin@gmail.com>
In-Reply-To: <20181013120409.1993-1-npiggin@gmail.com>
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To: Nicholas Piggin <npiggin@gmail.com>
Cc: "Gautham R . Shenoy" <ego@linux.vnet.ibm.com>, Mahesh Jagannath Salgaonkar <mahesh@linux.vnet.ibm.com>, kvm-ppc@vger.kernel.org, "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>, linuxppc-dev@lists.ozlabs.org, Akshay Adiga <akshay.adiga@linux.vnet.ibm.com>

On Sat, Oct 13, 2018 at 10:04:09PM +1000, Nicholas Piggin wrote:
> Reimplement Book3S idle code in C, moving POWER7/8/9 implementation
> speific HV idle code to the powernv platform code.
> 

[...]

> @@ -2760,21 +2744,47 @@ BEGIN_FTR_SECTION
>  	li	r4, LPCR_PECE_HVEE@higher
>  	sldi	r4, r4, 32
>  	or	r5, r5, r4
> -END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
> +FTR_SECTION_ELSE
> +	li	r3, PNV_THREAD_NAP
> +ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300)
>  	mtspr	SPRN_LPCR,r5
>  	isync
> -	li	r0, 0
> -	std	r0, HSTATE_SCRATCH0(r13)
> -	ptesync
> -	ld	r0, HSTATE_SCRATCH0(r13)
> -1:	cmpd	r0, r0
> -	bne	1b
> +
> +	mr	r0, r1
> +	ld	r1, PACAEMERGSP(r13)
> +	subi	r1, r1, STACK_FRAME_OVERHEAD
> +	std	r0, 0(r1)
> +	ld	r0, PACAR1(r13)
> +	std	r0, 8(r1)

This bit seems wrong to me.  If this is a secondary thread on POWER8,
we were already on the emergency stack, and now we've reset r1 back to
the top of the emergency stack and we're overwriting it.

I wonder why you didn't see secondary threads going off into lala land
in your tests?

Paul.