From mboxrd@z Thu Jan  1 00:00:00 1970
From: Paul Mackerras <paulus@ozlabs.org>
Date: Thu, 06 Jun 2019 21:55:20 +0000
Subject: Re: [PATCH v3 6/9] KVM: PPC: Ultravisor: Restrict flush of the partition tlb cache
Message-Id: <20190606215520.GA1220@blackberry>
List-Id: <kvm-ppc.vger.kernel.org>
References: <20190606173614.32090-1-cclaudio@linux.ibm.com>
 <20190606173614.32090-7-cclaudio@linux.ibm.com>
 <8736kmld0n.fsf@kermit.br.ibm.com>
In-Reply-To: <8736kmld0n.fsf@kermit.br.ibm.com>
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To: Murilo Opsfelder =?iso-8859-1?Q?Ara=FAjo?= <mopsfelder@gmail.com>
Cc: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>, Michael Anderson <andmike@linux.ibm.com>, Ram Pai <linuxram@us.ibm.com>, Claudio Carvalho <cclaudio@linux.ibm.com>, kvm-ppc@vger.kernel.org, Bharata B Rao <bharata@linux.ibm.com>, linuxppc-dev@ozlabs.org, Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>, Thiago Bauermann <bauermann@linux.ibm.com>, Anshuman Khandual <khandual@linux.vnet.ibm.com>

On Thu, Jun 06, 2019 at 04:39:04PM -0300, Murilo Opsfelder Ara=FAjo wrote:
> Claudio Carvalho <cclaudio@linux.ibm.com> writes:
>=20
> > From: Ram Pai <linuxram@us.ibm.com>
> >
> > Ultravisor is responsible for flushing the tlb cache, since it manages
> > the PATE entries. Hence skip tlb flush, if the ultravisor firmware is
> > available.
> >
> > Signed-off-by: Ram Pai <linuxram@us.ibm.com>
> > Signed-off-by: Claudio Carvalho <cclaudio@linux.ibm.com>
> > ---
> >  arch/powerpc/mm/book3s64/pgtable.c | 33 +++++++++++++++++-------------
> >  1 file changed, 19 insertions(+), 14 deletions(-)
> >
> > diff --git a/arch/powerpc/mm/book3s64/pgtable.c b/arch/powerpc/mm/book3=
s64/pgtable.c
> > index 40a9fc8b139f..1eeb5fe87023 100644
> > --- a/arch/powerpc/mm/book3s64/pgtable.c
> > +++ b/arch/powerpc/mm/book3s64/pgtable.c
> > @@ -224,6 +224,23 @@ void __init mmu_partition_table_init(void)
> >  	powernv_set_nmmu_ptcr(ptcr);
> >  }
> >
> > +static void flush_partition(unsigned int lpid, unsigned long dw0)
> > +{
> > +	if (dw0 & PATB_HR) {
> > +		asm volatile(PPC_TLBIE_5(%0, %1, 2, 0, 1) : :
> > +			     "r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));
> > +		asm volatile(PPC_TLBIE_5(%0, %1, 2, 1, 1) : :
> > +			     "r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));
> > +		trace_tlbie(lpid, 0, TLBIEL_INVAL_SET_LPID, lpid, 2, 0, 1);
> > +	} else {
> > +		asm volatile(PPC_TLBIE_5(%0, %1, 2, 0, 0) : :
> > +			     "r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));
> > +		trace_tlbie(lpid, 0, TLBIEL_INVAL_SET_LPID, lpid, 2, 0, 0);
> > +	}
> > +	/* do we need fixup here ?*/
> > +	asm volatile("eieio; tlbsync; ptesync" : : : "memory");
> > +}
> > +
>=20
> checkpatch.pl seems to complain:
>=20
> ERROR: need consistent spacing around '%' (ctx:WxV)
> #125: FILE: arch/powerpc/mm/book3s64/pgtable.c:230:
> +               asm volatile(PPC_TLBIE_5(%0, %1, 2, 0, 1) : :
>                                              ^
>=20
> ERROR: need consistent spacing around '%' (ctx:WxV)
> #127: FILE: arch/powerpc/mm/book3s64/pgtable.c:232:
> +               asm volatile(PPC_TLBIE_5(%0, %1, 2, 1, 1) : :
>                                              ^
>=20
> ERROR: need consistent spacing around '%' (ctx:WxV)
> #131: FILE: arch/powerpc/mm/book3s64/pgtable.c:236:
> +               asm volatile(PPC_TLBIE_5(%0, %1, 2, 0, 0) : :
>                                              ^

Then clearly checkpatch.pl has a bug.

Paul.