From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marc Zyngier Date: Fri, 13 Dec 2019 18:25:01 +0000 Subject: [PATCH 5/7] KVM: arm/arm64: Elide both CMOs and TBLIs on freeing the whole Stage-2 Message-Id: <20191213182503.14460-6-maz@kernel.org> List-Id: References: <20191213182503.14460-1-maz@kernel.org> In-Reply-To: <20191213182503.14460-1-maz@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: Cc: James Morse , Julien Thierry , Suzuki K Poulose , James Hogan , Paul Mackerras , Paolo Bonzini , =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= , Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, linux-mips@vger.kernel.org, kvm-ppc@vger.kernel.org, kvm@vger.kernel.org When freeing the whole of a VM's Stage-2 page tables, there is little point in doing cache maintenance on each and every page (the guest won't be running anymore, let alone having its MMU off). As for TLBs, there is no point in invalidating individual pages, as we can replace the whole thing with a VMALL operation, which invalidates all the TLBs for this VM in one go. Signed-off-by: Marc Zyngier --- virt/kvm/arm/mmu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/virt/kvm/arm/mmu.c b/virt/kvm/arm/mmu.c index 4399866842dc..d7c710491d26 100644 --- a/virt/kvm/arm/mmu.c +++ b/virt/kvm/arm/mmu.c @@ -1016,10 +1016,13 @@ void kvm_free_stage2_pgd(struct kvm *kvm) spin_lock(&kvm->mmu_lock); if (kvm->arch.pgd) { - unmap_stage2_range(kvm, 0, kvm_phys_size(kvm), 0); + unmap_stage2_range(kvm, 0, kvm_phys_size(kvm), + KVM_UNMAP_ELIDE_CMO | KVM_UNMAP_ELIDE_TBLI); pgd = READ_ONCE(kvm->arch.pgd); kvm->arch.pgd = NULL; kvm->arch.pgd_phys = 0; + + kvm_flush_remote_tlbs(kvm); } spin_unlock(&kvm->mmu_lock); -- 2.20.1