From mboxrd@z Thu Jan  1 00:00:00 1970
From: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Date: Wed, 18 Dec 2019 23:57:53 +0000
Subject: Re: [PATCH 1/2] powerpc/pseries/svm: Don't access some SPRs
Message-Id: <20191218235753.GA12285@us.ibm.com>
List-Id: <kvm-ppc.vger.kernel.org>
References: <20191218043048.3400-1-sukadev@linux.ibm.com>
 <875zidoqok.fsf@mpe.ellerman.id.au>
In-Reply-To: <875zidoqok.fsf@mpe.ellerman.id.au>
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To: Michael Ellerman <mpe@ellerman.id.au>
Cc: andmike@linux.ibm.com, linuxram@us.ibm.com, kvm-ppc@vger.kernel.org, linuxppc-dev@ozlabs.org, Sukadev Bhattiprolu <sukadev@linux.ibm.com>, bauerman@linux.ibm.com

Michael Ellerman [mpe@ellerman.id.au] wrote:
> 
> eg. here.
> 
> This is the fast path of context switch.
> 
> That expands to:
> 
> 	if (!(mfmsr() & MSR_S))
> 		asm volatile("mfspr %0, SPRN_BESCR" : "=r" (rval));
> 	if (!(mfmsr() & MSR_S))
> 		asm volatile("mfspr %0, SPRN_EBBHR" : "=r" (rval));
> 	if (!(mfmsr() & MSR_S))
> 		asm volatile("mfspr %0, SPRN_EBBRR" : "=r" (rval));
> 

Yes, should have optimized this at least :-)
> 
> If the Ultravisor is going to disable EBB and BHRB then we need new
> CPU_FTR bits for those, and the code that accesses those registers
> needs to be put behind cpu_has_feature(EBB) etc.

Will try the cpu_has_feature(). Would it be ok to use a single feature
bit, like UV or make it per-register group as that could need more
feature bits?

Thanks,

Sukadev