From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ram Pai Date: Sun, 26 Apr 2020 02:05:18 +0000 Subject: [PATCH v3] powerpc/XIVE: SVM: share the event-queue page with the Hypervisor. Message-Id: <20200426020518.GC5853@oc0525413822.ibm.com> List-Id: References: <1585211927-784-1-git-send-email-linuxram@us.ibm.com> In-Reply-To: <1585211927-784-1-git-send-email-linuxram@us.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: kvm-ppc@vger.kernel.org, linuxppc-dev@lists.ozlabs.org Cc: aik@ozlabs.ru, andmike@linux.ibm.com, groug@kaod.org, clg@fr.ibm.com, sukadev@linux.vnet.ibm.com, bauerman@linux.ibm.com, david@gibson.dropbear.id.au >From 10ea2eaf492ca3f22f67a5a63a2b7865e45299ad Mon Sep 17 00:00:00 2001 From: Ram Pai Date: Mon, 24 Feb 2020 01:09:48 -0500 Subject: [PATCH v3] powerpc/XIVE: SVM: share the event-queue page with the Hypervisor. XIVE interrupt controller uses an Event Queue (EQ) to enqueue event notifications when an exception occurs. The EQ is a single memory page provided by the O/S defining a circular buffer, one per server and priority couple. On baremetal, the EQ page is configured with an OPAL call. On pseries, an extra hop is necessary and the guest OS uses the hcall H_INT_SET_QUEUE_CONFIG to configure the XIVE interrupt controller. The XIVE controller being Hypervisor privileged, it will not be allowed to enqueue event notifications for a Secure VM unless the EQ pages are shared by the Secure VM. Hypervisor/Ultravisor still requires support for the TIMA and ESB page fault handlers. Until this is complete, QEMU can use the emulated XIVE device for Secure VMs, option "kernel_irqchip=off" on the QEMU pseries machine. Cc: kvm-ppc@vger.kernel.org Cc: linuxppc-dev@lists.ozlabs.org Cc: Michael Ellerman Cc: Thiago Jung Bauermann Cc: Michael Anderson Cc: Sukadev Bhattiprolu Cc: Alexey Kardashevskiy Cc: Paul Mackerras Cc: David Gibson Reviewed-by: Cedric Le Goater Reviewed-by: Greg Kurz Signed-off-by: Ram Pai v3: fix a minor semantics in description. and added reviewed-by from Cedric and Greg. v2: better description of the patch from Cedric. --- arch/powerpc/sysdev/xive/spapr.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/powerpc/sysdev/xive/spapr.c b/arch/powerpc/sysdev/xive/spapr.c index 55dc61c..608b52f 100644 --- a/arch/powerpc/sysdev/xive/spapr.c +++ b/arch/powerpc/sysdev/xive/spapr.c @@ -26,6 +26,8 @@ #include #include #include +#include +#include #include "xive-internal.h" @@ -501,6 +503,9 @@ static int xive_spapr_configure_queue(u32 target, struct xive_q *q, u8 prio, rc = -EIO; } else { q->qpage = qpage; + if (is_secure_guest()) + uv_share_page(PHYS_PFN(qpage_phys), + 1 << xive_alloc_order(order)); } fail: return rc; @@ -534,6 +539,8 @@ static void xive_spapr_cleanup_queue(unsigned int cpu, struct xive_cpu *xc, hw_cpu, prio); alloc_order = xive_alloc_order(xive_queue_shift); + if (is_secure_guest()) + uv_unshare_page(PHYS_PFN(__pa(q->qpage)), 1 << alloc_order); free_pages((unsigned long)q->qpage, alloc_order); q->qpage = NULL; } -- 1.8.3.1