From mboxrd@z Thu Jan 1 00:00:00 1970 From: Bharata B Rao Date: Tue, 23 Mar 2021 04:17:32 +0000 Subject: Re: [PATCH v6 3/6] KVM: PPC: Book3S HV: Add support for H_RPT_INVALIDATE Message-Id: <20210323040532.GA868309@in.ibm.com> List-Id: References: <20210311083939.595568-1-bharata@linux.ibm.com> <20210311083939.595568-4-bharata@linux.ibm.com> In-Reply-To: MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable To: David Gibson Cc: farosas@linux.ibm.com, aneesh.kumar@linux.ibm.com, npiggin@gmail.com, kvm-ppc@vger.kernel.org, linuxppc-dev@lists.ozlabs.org On Tue, Mar 23, 2021 at 01:26:56PM +1100, David Gibson wrote: > On Thu, Mar 11, 2021 at 02:09:36PM +0530, Bharata B Rao wrote: > > H_RPT_INVALIDATE does two types of TLB invalidations: > >=20 > > 1. Process-scoped invalidations for guests when LPCR[GTSE]=3D0. > > This is currently not used in KVM as GTSE is not usually > > disabled in KVM. > > 2. Partition-scoped invalidations that an L1 hypervisor does on > > behalf of an L2 guest. This is currently handled > > by H_TLB_INVALIDATE hcall and this new replaces the old that. > >=20 > > This commit enables process-scoped invalidations for L1 guests. > > Support for process-scoped and partition-scoped invalidations > > from/for nested guests will be added separately. > >=20 > > Process scoped tlbie invalidations from L1 and nested guests > > need RS register for TLBIE instruction to contain both PID and > > LPID. This patch introduces primitives that execute tlbie > > instruction with both PID and LPID set in prepartion for > > H_RPT_INVALIDATE hcall. > >=20 > > A description of H_RPT_INVALIDATE follows: > >=20 > > int64=A0=A0 /* H_Success: Return code on successful completion */ > > =A0=A0=A0=A0=A0=A0=A0 /* H_Busy - repeat the call with the same */ > > =A0=A0=A0=A0=A0=A0=A0 /* H_Parameter, H_P2, H_P3, H_P4, H_P5 : Invalid > > parameters */ > > hcall(const uint64 H_RPT_INVALIDATE, /* Invalidate RPT > > translation > > lookaside information */ > > =A0=A0=A0=A0=A0 uint64 id,=A0 =A0=A0=A0=A0=A0 /* PID/LPID to invalidate= */ > > =A0=A0=A0=A0=A0 uint64 target,=A0=A0=A0 /* Invalidation target */ > > =A0=A0=A0=A0=A0 uint64 type,=A0=A0=A0=A0=A0 /* Type of lookaside inform= ation */ > > =A0=A0=A0=A0=A0 uint64 pg_sizes, /* Page sizes */ > > =A0=A0=A0=A0=A0 uint64 start,=A0=A0=A0=A0 /* Start of Effective Address= (EA) > > range (inclusive) */ > > =A0=A0=A0=A0=A0 uint64 end)=A0=A0=A0=A0=A0=A0 /* End of EA range (exclu= sive) */ > >=20 > > Invalidation targets (target) > > ----------------------------- > > Core MMU=A0=A0=A0=A0=A0=A0=A0 0x01 /* All virtual processors in the > > partition */ > > Core local MMU=A0 0x02 /* Current virtual processor */ > > Nest MMU=A0=A0=A0=A0=A0=A0=A0 0x04 /* All nest/accelerator agents > > in use by the partition */ > >=20 > > A combination of the above can be specified, > > except core and core local. > >=20 > > Type of translation to invalidate (type) > > --------------------------------------- > > NESTED=A0=A0=A0=A0=A0=A0 0x0001=A0 /* invalidate nested guest partition= -scope */ > > TLB=A0=A0=A0=A0=A0=A0=A0=A0=A0=A00x0002=A0 /* Invalidate TLB */ > > PWC=A0=A0=A0=A0=A0=A0=A0=A0=A0=A00x0004=A0 /* Invalidate Page Walk Cach= e */ > > PRT=A0=A0=A0=A0=A0=A0=A0=A0=A0=A00x0008=A0 /* Invalidate caching of Pro= cess Table > > Entries if NESTED is clear */ > > PAT=A0=A0=A0=A0=A0=A0=A0=A0=A0=A00x0008=A0 /* Invalidate caching of Par= tition Table > > Entries if NESTED is set */ > >=20 > > A combination of the above can be specified. > >=20 > > Page size mask (pages) > > ---------------------- > > 4K=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 0x01 > > 64K=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 0x02 > > 2M=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 0x04 > > 1G=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 0x08 > > All sizes=A0=A0=A0=A0=A0=A0 (-1UL) > >=20 > > A combination of the above can be specified. > > All page sizes can be selected with -1. > >=20 > > Semantics: Invalidate radix tree lookaside information > > =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 matching the parameters given. > > * Return H_P2, H_P3 or H_P4 if target, type, or pageSizes parameters > > are different from the defined values. > > * Return H_PARAMETER if NESTED is set and pid is not a valid nested > > LPID allocated to this partition > > * Return H_P5 if (start, end) doesn't form a valid range. Start and > > end should be a valid Quadrant address and=A0 end > start. > > * Return H_NotSupported if the partition is not in running in radix > > translation mode. > > * May invalidate more translation information than requested. > > * If start =3D 0 and end =3D -1, set the range to cover all valid > > addresses. Else start and end should be aligned to 4kB (lower 11 > > bits clear). > > * If NESTED is clear, then invalidate process scoped lookaside > > information. Else pid specifies a nested LPID, and the invalidation > > is performed =A0 on nested guest partition table and nested guest > > partition scope real addresses. > > * If pid =3D 0 and NESTED is clear, then valid addresses are quadrant 3 > > and quadrant 0 spaces, Else valid addresses are quadrant 0. > > * Pages which are fully covered by the range are to be invalidated. > > =A0 Those which are partially covered are considered outside > > invalidation range, which allows a caller to optimally invalidate > > ranges that may =A0 contain mixed page sizes. > > * Return H_SUCCESS on success. > >=20 > > Signed-off-by: Bharata B Rao >=20 > Reviewed-by: David Gibson >=20 > with the exception of one nit noted below. >=20 > > --- > > .../include/asm/book3s/64/tlbflush-radix.h | 4 + > > arch/powerpc/include/asm/mmu_context.h | 11 ++ > > arch/powerpc/kvm/book3s_hv.c | 46 ++++++ > > arch/powerpc/mm/book3s64/radix_tlb.c | 152 +++++++++++++++++- > > 4 files changed, 209 insertions(+), 4 deletions(-) > >=20 > > diff --git a/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h b/arch= /powerpc/include/asm/book3s/64/tlbflush-radix.h > > index 8b33601cdb9d..a46fd37ad552 100644 > > --- a/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h > > +++ b/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h > > @@ -4,6 +4,10 @@ > > =20 > > #include > > =20 > > +#define RIC_FLUSH_TLB 0 > > +#define RIC_FLUSH_PWC 1 > > +#define RIC_FLUSH_ALL 2 >=20 > Is there a reason for moving these? You don't appear to be adding a > use of them outside the .c file they were in before. They are used in arch/powerpc/kvm/book3s_hv_nested.c. It was all in the same patchset earlier, but during reorgazing the hcall into 3 separate patc= hes, this change remained here. May be I should move this change to the next pat= ch where it is used. Thanks for your review. Regards, Bharata.