Re: Question about removing memslots

Avi Kivity
2012-03-28T10:51:36Z

On 03/28/2012 12:17 PM, Benjamin Herrenschmidt wrote:
> On Wed, 2012-03-28 at 12:05 +0200, Avi Kivity wrote:
>
> > That's strange, the cirrus BAR allows the framebuffer and bitblt region
> > to coexist:
> >
> > 0000000000000000-7ffffffffffffffe (prio 0, RW): pci
> > 00000000000a0000-00000000000bffff (prio 1, RW): cirrus-lowmem-container
> > 00000000000a0000-00000000000a7fff (prio 1, RW): alias vga.bank0
> > @vga.vram 0000000000000000-0000000000007fff
> > 00000000000a0000-00000000000bffff (prio 0, RW): cirrus-low-memory
> > 00000000000a8000-00000000000affff (prio 1, RW): alias vga.bank1
> > @vga.vram
> >
> > ^ those are continuously flipped when running 16-bit software
> >
> > 0000000000008000-000000000000ffff
> > 00000000000c0000-00000000000dffff (prio 1, RW): pc.rom
> > 00000000000e0000-00000000000fffff (prio 1, R-): isa-bios
> > 00000000fc000000-00000000fdffffff (prio 1, RW): cirrus-pci-bar0
> > 00000000fc000000-00000000fc7fffff (prio 1, RW): vga.vram
> > 00000000fc000000-00000000fc7fffff (prio 0, RW): cirrus-linear-io
> > 00000000fd000000-00000000fd3fffff (prio 0, RW): cirrus-bitblt-mmio
> >
> > ^ the cirrus BAR, write to 0xfc000000 and you hit vga.vram, write to
> > 0xfd000000 and you trigger a bitblt.
> >
> > 00000000feba0000-00000000febbffff (prio 1, RW): e1000-mmio
> > 00000000febf0000-00000000febf0fff (prio 1, RW): cirrus-mmio
> >
> > A guest driver problem perhaps?
>
> Quite possibly, I'm not familiar with the cirrus HW. The trigger is an
> MMIO register write done by cirrusfb, which causes
> cirrus_update_memory_access() to switch the BAR to emulation as a result
> of this becoming true:
>
> s->cirrus_srcptr != s->cirrus_srcptr_end
>
> I haven't had a chance to dig further today (I'm home now), I can have a
> look tomorrow.
>

Ah, then it's not a guest problem, it's how the chip was designed.
Newer chips do allow a workaround (GR31 bit 6):

6 System Source Location (Revision A): If this bit is ‘1’, the CL-GD546X
responds to write accesses at 000BC000h–000BFFFFh for color-expand
BitBLTs. This frees the linear address apertures for other, concurrent
accesses. If this bit is ‘0’, the CL-GD546X uses the linear aperture for
BitBLTs (compatible with CL-GD543X/’4X).
System Source Location (Revision B): If this bit is ‘1’,
system-to-screen BitBLTs use the second 16-Mbyte window specified in
PCI10. This allows direct frame buffer accesses in the first window to
be mixed with system-to-screen writes in the second window without
restrictions.

If a system-to-screen BitBLT requiring data is not active, writes to the
second window complete in the minimum time and the data is discarded.
Writes to the first window are ignored by the BitBLT engine (but are
taken as direct writes to the frame buffer).

If this bit is ‘0’, system-to-screen BitBLTs use the first 16-Mbyte
window (compatible with CL-GD543X/’4X).

But it looks like this refers to 546x, even though I found it in the
5446 manual.

--
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