From mboxrd@z Thu Jan 1 00:00:00 1970 From: Scott Wood Date: Tue, 26 Jun 2012 22:24:08 +0000 Subject: Re: [RFC PATCH 13/17] PowerPC: booke64: Use SPRG0/3 scratch for bolted TLB miss & crit int Message-Id: <4FEA3688.5030603@freescale.com> List-Id: References: <1340627195-11544-1-git-send-email-mihai.caraman@freescale.com> <1340627195-11544-14-git-send-email-mihai.caraman@freescale.com> In-Reply-To: <1340627195-11544-14-git-send-email-mihai.caraman@freescale.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: Mihai Caraman Cc: kvm-ppc@vger.kernel.org, kvm@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, qemu-ppc@nongnu.org On 06/25/2012 07:26 AM, Mihai Caraman wrote: > Embedded.Hypervisor category defines GSPRG0..3 physical registers for guests. > Avoid SPRG4-7 usage as scratch in host exception handlers, otherwise guest > SPRG4-7 registers will be clobbered. > For bolted TLB miss exception handlers, which is the version currently > supported by KVM, use SPRN_SPRG_GEN_SCRATCH (aka SPRG0) instead of > SPRN_SPRG_TLB_SCRATCH (aka SPRG6) and replace TLB with GEN PACA slots to > keep consitency. > For critical exception handler use SPRG3 instead of SPRG7. extlb is in the same cache line as other TLB stuff we need, while exgen isn't. Let's stick with extlb. -Scott