From mboxrd@z Thu Jan 1 00:00:00 1970 From: janani Date: Mon, 08 Jul 2019 17:38:32 +0000 Subject: Re: [PATCH v4 1/8] KVM: PPC: Ultravisor: Introduce the MSR_S bit Message-Id: List-Id: References: <20190628200825.31049-1-cclaudio@linux.ibm.com> <20190628200825.31049-2-cclaudio@linux.ibm.com> In-Reply-To: <20190628200825.31049-2-cclaudio@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: Claudio Carvalho Cc: Madhavan Srinivasan , Michael Anderson , Ram Pai , kvm-ppc@vger.kernel.org, Bharata B Rao , linuxppc-dev@ozlabs.org, Ryan Grimm , Sukadev Bhattiprolu , Thiago Bauermann , Anshuman Khandual On 2019-06-28 15:08, Claudio Carvalho wrote: > From: Sukadev Bhattiprolu > > The ultravisor processor mode is introduced in POWER platforms that > supports the Protected Execution Facility (PEF). Ultravisor is higher > privileged than hypervisor mode. > > In PEF enabled platforms, the MSR_S bit is used to indicate if the > thread is in secure state. With the MSR_S bit, the privilege state of > the thread is now determined by MSR_S, MSR_HV and MSR_PR, as follows: > > S HV PR > ----------------------- > 0 x 1 problem > 1 0 1 problem > x x 0 privileged > x 1 0 hypervisor > 1 1 0 ultravisor > 1 1 1 reserved > > The hypervisor doesn't (and can't) run with the MSR_S bit set, but a > secure guest and the ultravisor firmware do. > > Signed-off-by: Sukadev Bhattiprolu > Signed-off-by: Ram Pai > [ Update the commit message ] > Signed-off-by: Claudio Carvalho Reviewed-by: Janani Janakiraman > --- > arch/powerpc/include/asm/reg.h | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/arch/powerpc/include/asm/reg.h > b/arch/powerpc/include/asm/reg.h > index 10caa145f98b..39b4c0a519f5 100644 > --- a/arch/powerpc/include/asm/reg.h > +++ b/arch/powerpc/include/asm/reg.h > @@ -38,6 +38,7 @@ > #define MSR_TM_LG 32 /* Trans Mem Available */ > #define MSR_VEC_LG 25 /* Enable AltiVec */ > #define MSR_VSX_LG 23 /* Enable VSX */ > +#define MSR_S_LG 22 /* Secure VM bit */ > #define MSR_POW_LG 18 /* Enable Power Management */ > #define MSR_WE_LG 18 /* Wait State Enable */ > #define MSR_TGPR_LG 17 /* TLB Update registers in use */ > @@ -71,11 +72,13 @@ > #define MSR_SF __MASK(MSR_SF_LG) /* Enable 64 bit mode */ > #define MSR_ISF __MASK(MSR_ISF_LG) /* Interrupt 64b mode valid on 630 > */ > #define MSR_HV __MASK(MSR_HV_LG) /* Hypervisor state */ > +#define MSR_S __MASK(MSR_S_LG) /* Secure state */ > #else > /* so tests for these bits fail on 32-bit */ > #define MSR_SF 0 > #define MSR_ISF 0 > #define MSR_HV 0 > +#define MSR_S 0 > #endif > > /*