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From: Andrew Jones <ajones@ventanamicro.com>
To: kvm-riscv@lists.infradead.org
Subject: [PATCH v2 5/6] RISCV: KVM: Add sstateen0 context save/restore
Date: Fri, 21 Jul 2023 11:04:46 +0200	[thread overview]
Message-ID: <20230721-78d78a037c03f7a75c5e6525@orel> (raw)
In-Reply-To: <20230721075439.454473-6-mchitale@ventanamicro.com>

On Fri, Jul 21, 2023 at 01:24:38PM +0530, Mayuresh Chitale wrote:
> Define sstateen0 and add sstateen0 save/restore for guest VCPUs.
> 
> Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
> ---
>  arch/riscv/include/asm/csr.h      |  1 +
>  arch/riscv/include/asm/kvm_host.h |  8 ++++++++
>  arch/riscv/kvm/vcpu.c             | 10 ++++++++++
>  3 files changed, 19 insertions(+)
> 
> diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
> index b52270278733..5168f37d8e75 100644
> --- a/arch/riscv/include/asm/csr.h
> +++ b/arch/riscv/include/asm/csr.h
> @@ -286,6 +286,7 @@
>  #define CSR_STVEC		0x105
>  #define CSR_SCOUNTEREN		0x106
>  #define CSR_SENVCFG		0x10a
> +#define CSR_SSTATEEN0		0x10c
>  #define CSR_SSCRATCH		0x140
>  #define CSR_SEPC		0x141
>  #define CSR_SCAUSE		0x142
> diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h
> index c3cc0cb39cf8..c9837772b109 100644
> --- a/arch/riscv/include/asm/kvm_host.h
> +++ b/arch/riscv/include/asm/kvm_host.h
> @@ -170,6 +170,10 @@ struct kvm_vcpu_config {
>  	u64 hstateen0;
>  };
>  
> +struct kvm_vcpu_smstateen_csr {
> +	unsigned long sstateen0;
> +};
> +
>  struct kvm_vcpu_arch {
>  	/* VCPU ran at least once */
>  	bool ran_atleast_once;
> @@ -190,6 +194,7 @@ struct kvm_vcpu_arch {
>  	unsigned long host_stvec;
>  	unsigned long host_scounteren;
>  	unsigned long host_senvcfg;
> +	unsigned long host_sstateen0;
>  
>  	/* CPU context of Host */
>  	struct kvm_cpu_context host_context;
> @@ -200,6 +205,9 @@ struct kvm_vcpu_arch {
>  	/* CPU CSR context of Guest VCPU */
>  	struct kvm_vcpu_csr guest_csr;
>  
> +	/* CPU Smstateen CSR context of Guest VCPU */
> +	struct kvm_vcpu_smstateen_csr smstateen_csr;
> +
>  	/* CPU context upon Guest VCPU reset */
>  	struct kvm_cpu_context guest_reset_context;
>  
> diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
> index 37f1ed70d782..ae750decbefe 100644
> --- a/arch/riscv/kvm/vcpu.c
> +++ b/arch/riscv/kvm/vcpu.c
> @@ -1138,14 +1138,24 @@ static void kvm_riscv_update_hvip(struct kvm_vcpu *vcpu)
>   */
>  static void noinstr kvm_riscv_vcpu_enter_exit(struct kvm_vcpu *vcpu)
>  {
> +	struct kvm_vcpu_smstateen_csr *smcsr = &vcpu->arch.smstateen_csr;
>  	struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
> +	struct kvm_vcpu_config *cfg = &vcpu->arch.cfg;
>  
>  	vcpu->arch.host_senvcfg = csr_swap(CSR_SENVCFG, csr->senvcfg);
> +	if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN) &&
> +	    (cfg->hstateen0 & SMSTATEEN0_SSTATEEN0))
> +		vcpu->arch.host_sstateen0 = csr_swap(CSR_SSTATEEN0,
> +						     smcsr->sstateen0);
>  	guest_state_enter_irqoff();
>  	__kvm_riscv_switch_to(&vcpu->arch);
>  	vcpu->arch.last_exit_cpu = vcpu->cpu;
>  	guest_state_exit_irqoff();
>  	csr->senvcfg = csr_swap(CSR_SENVCFG, vcpu->arch.host_senvcfg);
> +	if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN) &&
> +	    (cfg->hstateen0 & SMSTATEEN0_SSTATEEN0))
> +		smcsr->sstateen0 = csr_swap(CSR_SSTATEEN0,
> +					    vcpu->arch.host_sstateen0);
>  }

It might be nice to keep kvm_riscv_vcpu_enter_exit() "clean", by adding
a couple functions. Something like

 static __always_inline void kvm_riscv_vcpu_swap_in_guest_state(struct kvm_vcpu *vcpu)
 {
   struct kvm_vcpu_smstateen_csr *smcsr = &vcpu->arch.smstateen_csr;
   struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
   struct kvm_vcpu_config *cfg = &vcpu->arch.cfg;

   vcpu->arch.host_senvcfg = csr_swap(CSR_SENVCFG, csr->senvcfg);
   if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN) &&
       (cfg->hstateen0 & SMSTATEEN0_SSTATEEN0))
          vcpu->arch.host_sstateen0 = csr_swap(CSR_SSTATEEN0,
                                               smcsr->sstateen0);
 }

 static __always_inline void kvm_riscv_vcpu_swap_in_host_state(struct kvm_vcpu *vcpu)
 {
   struct kvm_vcpu_smstateen_csr *smcsr = &vcpu->arch.smstateen_csr;
   struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
   struct kvm_vcpu_config *cfg = &vcpu->arch.cfg;

   csr->senvcfg = csr_swap(CSR_SENVCFG, vcpu->arch.host_senvcfg);
   if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN) &&
       (cfg->hstateen0 & SMSTATEEN0_SSTATEEN0))
           smcsr->sstateen0 = csr_swap(CSR_SSTATEEN0,
                                       vcpu->arch.host_sstateen0);
 }

 static void noinstr kvm_riscv_vcpu_enter_exit(struct kvm_vcpu *vcpu)
 {
    kvm_riscv_vcpu_swap_in_guest_state(vcpu);
    guest_state_enter_irqoff();
    __kvm_riscv_switch_to(&vcpu->arch);
    vcpu->arch.last_exit_cpu = vcpu->cpu;
    guest_state_exit_irqoff();
    kvm_riscv_vcpu_swap_in_host_state(vcpu);
 }

>  
>  int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
> -- 
> 2.34.1
>

Either way,

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

Thanks,
drew


  reply	other threads:[~2023-07-21  9:04 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-21  7:54 [PATCH v2 0/6] Risc-V Kvm Smstateen Mayuresh Chitale
2023-07-21  7:54 ` [PATCH v2 1/6] RISC-V: Detect Smstateen extension Mayuresh Chitale
2023-07-21  8:49   ` Andrew Jones
2023-07-21  9:07     ` Conor Dooley
2023-07-21 10:11   ` Krzysztof Kozlowski
2023-07-21  7:54 ` [PATCH v2 2/6] RISC-V: KVM: Add kvm_vcpu_config Mayuresh Chitale
2023-07-21  8:53   ` Andrew Jones
2023-07-21  7:54 ` [PATCH v2 3/6] RISC-V: KVM: Enable Smstateen accesses Mayuresh Chitale
2023-07-21  8:54   ` Andrew Jones
2023-07-21  7:54 ` [PATCH v2 4/6] RISCV: KVM: Add senvcfg context save/restore Mayuresh Chitale
2023-07-21  8:55   ` Andrew Jones
2023-07-21  7:54 ` [PATCH v2 5/6] RISCV: KVM: Add sstateen0 " Mayuresh Chitale
2023-07-21  9:04   ` Andrew Jones [this message]
2023-07-21  7:54 ` [PATCH v2 6/6] RISCV: KVM: Add sstateen0 to ONE_REG Mayuresh Chitale
2023-07-21  9:13   ` Andrew Jones

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