From: Andrew Jones <ajones@ventanamicro.com>
To: kvm-riscv@lists.infradead.org
Subject: [PATCH v2 3/8] tools: riscv: Add header file csr.h
Date: Wed, 6 Sep 2023 15:47:31 +0200 [thread overview]
Message-ID: <20230906-11348d34e52289c8f52be8f9@orel> (raw)
In-Reply-To: <CAJve8ok-Z6VCziFj5t0=BoouZ-VLyGaqEng-dYGTFnP-CR36kw@mail.gmail.com>
On Wed, Sep 06, 2023 at 05:09:20PM +0800, Haibo Xu wrote:
> On Wed, Sep 6, 2023 at 3:13?PM Andrew Jones <ajones@ventanamicro.com> wrote:
> >
> > On Wed, Sep 06, 2023 at 02:35:42PM +0800, Haibo Xu wrote:
> > > On Mon, Sep 4, 2023 at 9:33?PM Andrew Jones <ajones@ventanamicro.com> wrote:
> > > >
> > > > On Sat, Sep 02, 2023 at 08:59:25PM +0800, Haibo Xu wrote:
> > > > > Borrow the csr definitions and operations from kernel's
> > > > > arch/riscv/include/asm/csr.h to tools/ for riscv.
> > > > >
> > > > > Signed-off-by: Haibo Xu <haibo1.xu@intel.com>
> > > > > ---
> > > > > tools/arch/riscv/include/asm/csr.h | 521 +++++++++++++++++++++++++++++
> > > > > 1 file changed, 521 insertions(+)
> > > > > create mode 100644 tools/arch/riscv/include/asm/csr.h
> > > > >
> > > > > diff --git a/tools/arch/riscv/include/asm/csr.h b/tools/arch/riscv/include/asm/csr.h
> > > > > new file mode 100644
> > > > > index 000000000000..4e86c82aacbd
> > > > > --- /dev/null
> > > > > +++ b/tools/arch/riscv/include/asm/csr.h
> > > > > @@ -0,0 +1,521 @@
> > > > > +/* SPDX-License-Identifier: GPL-2.0-only */
> > > > > +/*
> > > > > + * Copyright (C) 2015 Regents of the University of California
> > > > > + */
> > > > > +
> > > > > +#ifndef _ASM_RISCV_CSR_H
> > > > > +#define _ASM_RISCV_CSR_H
> > > > > +
> > > > > +#include <linux/bits.h>
> > > > > +
> > > > > +/* Status register flags */
> > > > > +#define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */
> > > > > +#define SR_MIE _AC(0x00000008, UL) /* Machine Interrupt Enable */
> > > > > +#define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */
> > > > > +#define SR_MPIE _AC(0x00000080, UL) /* Previous Machine IE */
> > > > > +#define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */
> > > > > +#define SR_MPP _AC(0x00001800, UL) /* Previously Machine */
> > > > > +#define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */
> > > > > +
> > > > > +#define SR_FS _AC(0x00006000, UL) /* Floating-point Status */
> > > > > +#define SR_FS_OFF _AC(0x00000000, UL)
> > > > > +#define SR_FS_INITIAL _AC(0x00002000, UL)
> > > > > +#define SR_FS_CLEAN _AC(0x00004000, UL)
> > > > > +#define SR_FS_DIRTY _AC(0x00006000, UL)
> > > > > +
> > > > > +#define SR_VS _AC(0x00000600, UL) /* Vector Status */
> > > > > +#define SR_VS_OFF _AC(0x00000000, UL)
> > > > > +#define SR_VS_INITIAL _AC(0x00000200, UL)
> > > > > +#define SR_VS_CLEAN _AC(0x00000400, UL)
> > > > > +#define SR_VS_DIRTY _AC(0x00000600, UL)
> > > > > +
> > > > > +#define SR_XS _AC(0x00018000, UL) /* Extension Status */
> > > > > +#define SR_XS_OFF _AC(0x00000000, UL)
> > > > > +#define SR_XS_INITIAL _AC(0x00008000, UL)
> > > > > +#define SR_XS_CLEAN _AC(0x00010000, UL)
> > > > > +#define SR_XS_DIRTY _AC(0x00018000, UL)
> > > > > +
> > > > > +#define SR_FS_VS (SR_FS | SR_VS) /* Vector and Floating-Point Unit */
> > > > > +
> > > > > +#ifndef CONFIG_64BIT
> > > >
> > > > How do we ensure CONFIG_64BIT is set?
> > > >
> > >
> > > Currently, no explicit checking for this.
> > > Shall we add a gatekeeper in this file to ensure it is set?
> >
> > Not in this file, since this file is shared by all the tools and...
> >
> > >
> > > #ifndef CONFIG_64BIT
> > > #error "CONFIG_64BIT was not set"
> > > #endif
> >
> > ...we'll surely hit this error right now since nothing is setting
> > CONFIG_64BIT when compiling KVM selftests.
> >
> > We need to define CONFIG_64BIT in the build somewhere prior to any
> > headers which depend on it being included. Maybe we can simply
> > add -DCONFIG_64BIT to CFLAGS, since all KVM selftests supported
> > architectures are 64-bit.
> >
>
> Make sense! Another option can be just add "#define CONFIG_64BIT" at
> the begin of csr.h
Nope, other tools/tests may want to include csr.h someday and they may or
may not be targeting 64-bit. They'll need to appropriately set
CONFIG_64BIT themselves. We could require
#define CONFIG_64BIT
#include <asm/csr.h>
everywhere we include it, but that's error prone since it'll get forgotten
and nothing will complain unless a define which isn't also present in
!CONFIG_64BIT is used.
Thanks,
drew
next prev parent reply other threads:[~2023-09-06 13:47 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-02 12:59 [PATCH v2 0/8] RISCV: Add kvm Sstc timer selftest Haibo Xu
2023-09-02 12:59 ` [PATCH v2 1/8] KVM: selftests: Unify the codes for guest exception handling Haibo Xu
2023-09-04 11:15 ` Andrew Jones
2023-09-06 2:15 ` Haibo Xu
2023-09-02 12:59 ` [PATCH v2 2/8] KVM: arm64: selftest: Split arch_timer test code Haibo Xu
2023-09-04 13:24 ` Andrew Jones
2023-09-06 2:14 ` Haibo Xu
2023-09-06 3:44 ` Haibo Xu
2023-09-06 7:01 ` Andrew Jones
2023-09-06 9:01 ` Haibo Xu
2023-09-06 6:41 ` Andrew Jones
2023-09-06 6:58 ` Haibo Xu
2023-09-02 12:59 ` [PATCH v2 3/8] tools: riscv: Add header file csr.h Haibo Xu
2023-09-04 13:26 ` Andrew Jones
2023-09-04 13:33 ` Andrew Jones
2023-09-06 6:35 ` Haibo Xu
2023-09-06 7:13 ` Andrew Jones
2023-09-06 9:09 ` Haibo Xu
2023-09-06 13:47 ` Andrew Jones [this message]
2023-09-02 12:59 ` [PATCH v2 4/8] KVM: riscv: selftests: Switch to use macro from csr.h Haibo Xu
2023-09-04 13:31 ` Andrew Jones
2023-09-06 6:56 ` Haibo Xu
2023-09-02 12:59 ` [PATCH v2 5/8] KVM: riscv: selftests: Add exception handling support Haibo Xu
2023-09-04 13:46 ` Andrew Jones
2023-09-02 12:59 ` [PATCH v2 6/8] KVM: riscv: selftests: Add guest helper to get vcpu id Haibo Xu
2023-09-04 13:48 ` Andrew Jones
2023-09-02 12:59 ` [PATCH v2 7/8] KVM: riscv: selftest: Change vcpu_has_ext to a common function Haibo Xu
2023-09-04 14:04 ` Andrew Jones
2023-09-06 10:10 ` Haibo Xu
2023-09-07 3:57 ` Haibo Xu
2023-09-07 9:01 ` Andrew Jones
2023-09-07 9:18 ` Haibo Xu
2023-09-02 12:59 ` [PATCH v2 8/8] KVM: riscv: selftests: Add sstc timer test Haibo Xu
2023-09-04 14:58 ` Andrew Jones
2023-09-07 4:20 ` Haibo Xu
2023-09-07 19:01 ` Andrew Jones
2023-09-08 1:19 ` Haibo Xu
2023-09-08 2:36 ` Haibo Xu
2023-09-05 10:36 ` [PATCH v2 0/8] RISCV: Add kvm Sstc timer selftest Andrew Jones
2023-09-06 1:23 ` Haibo Xu
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