From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andrew Jones Date: Mon, 25 Sep 2023 16:13:40 +0200 Subject: [PATCH v2 4/9] RISC-V: Detect Zicond from ISA string In-Reply-To: <20230925133859.1735879-5-apatel@ventanamicro.com> References: <20230925133859.1735879-1-apatel@ventanamicro.com> <20230925133859.1735879-5-apatel@ventanamicro.com> Message-ID: <20230925-434ad7cfaea0011fe0fb9989@orel> List-Id: To: kvm-riscv@lists.infradead.org MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit On Mon, Sep 25, 2023 at 07:08:54PM +0530, Anup Patel wrote: > The RISC-V integer conditional (Zicond) operation extension defines > standard conditional arithmetic and conditional-select/move operations > which are inspired from the XVentanaCondOps extension. In fact, QEMU > RISC-V also has support for emulating Zicond extension. > > Let us detect Zicond extension from ISA string available through > DT or ACPI. > > Signed-off-by: Anup Patel > --- > arch/riscv/include/asm/hwcap.h | 1 + > arch/riscv/kernel/cpufeature.c | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > index b7efe9e2fa89..15bafc02ffd4 100644 > --- a/arch/riscv/include/asm/hwcap.h > +++ b/arch/riscv/include/asm/hwcap.h > @@ -60,6 +60,7 @@ > #define RISCV_ISA_EXT_ZIHPM 42 > #define RISCV_ISA_EXT_SMSTATEEN 43 > #define RISCV_ISA_EXT_XVENTANACONDOPS 44 > +#define RISCV_ISA_EXT_ZICOND 45 > > #define RISCV_ISA_EXT_MAX 64 > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index 3a31d34fe709..7f683916f2c2 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -167,6 +167,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { > __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), > __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ), > __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR), > + __RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND), > __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR), > __RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI), > __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), > -- > 2.34.1 > Reviewed-by: Andrew Jones