From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andrew Jones Date: Mon, 25 Sep 2023 16:11:39 +0200 Subject: [PATCH v2 1/9] dt-bindings: riscv: Add XVentanaCondOps extension entry In-Reply-To: <20230925133859.1735879-2-apatel@ventanamicro.com> References: <20230925133859.1735879-1-apatel@ventanamicro.com> <20230925133859.1735879-2-apatel@ventanamicro.com> Message-ID: <20230925-e2aee59a5ea91fa14fab12ed@orel> List-Id: To: kvm-riscv@lists.infradead.org MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit On Mon, Sep 25, 2023 at 07:08:51PM +0530, Anup Patel wrote: > Add an entry for the XVentanaCondOps extension to the > riscv,isa-extensions property. > > Signed-off-by: Anup Patel > --- > Documentation/devicetree/bindings/riscv/extensions.yaml | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml > index 36ff6749fbba..cad8ef68eca7 100644 > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml > @@ -171,6 +171,13 @@ properties: > memory types as ratified in the 20191213 version of the privileged > ISA specification. > > + - const: xventanacondops > + description: | > + The Ventana specific XVentanaCondOps extension for conditional > + arithmetic and conditional-select/move operations defined by the > + Ventana custom extensions specification v1.0.1 (or higher) at > + https://github.com/ventanamicro/ventana-custom-extensions/releases. > + > - const: zba > description: | > The standard Zba bit-manipulation extension for address generation > -- > 2.34.1 > Reviewed-by: Andrew Jones