From: Conor Dooley <conor@kernel.org>
To: kvm-riscv@lists.infradead.org
Subject: [PATCH v2 0/9] KVM RISC-V Conditional Operations
Date: Mon, 25 Sep 2023 16:36:56 +0100 [thread overview]
Message-ID: <20230925-reappear-unkind-7f31acdd82de@spud> (raw)
In-Reply-To: <20230925-gorged-boxer-3804735e2d18@spud>
On Mon, Sep 25, 2023 at 04:33:15PM +0100, Conor Dooley wrote:
> On Mon, Sep 25, 2023 at 07:08:50PM +0530, Anup Patel wrote:
> > This series extends KVM RISC-V to allow Guest/VM discover and use
> > conditional operations related ISA extensions (namely XVentanaCondOps
> > and Zicond).
> >
> > To try these patches, use KVMTOOL from riscv_zbx_zicntr_smstateen_condops_v1
> > branch at: https://github.com/avpatel/kvmtool.git
> >
> > These patches are based upon the latest riscv_kvm_queue and can also be
> > found in the riscv_kvm_condops_v2 branch at:
> > https://github.com/avpatel/linux.git
> >
> > Changes since v1:
> > - Rebased the series on riscv_kvm_queue
> > - Split PATCH1 and PATCH2 of v1 series into two patches
> > - Added separate test configs for XVentanaCondOps and Zicond in PATCH7
> > of v1 series.
> >
> > Anup Patel (9):
> > dt-bindings: riscv: Add XVentanaCondOps extension entry
> > RISC-V: Detect XVentanaCondOps from ISA string
> > dt-bindings: riscv: Add Zicond extension entry
> > RISC-V: Detect Zicond from ISA string
>
> For these 4:
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Actually, now that I think of it, I'm going to temporarily un-review this.
From patch-acceptance.rst:
| Additionally, the RISC-V specification allows implementers to create
| their own custom extensions. These custom extensions aren't required
| to go through any review or ratification process by the RISC-V
| Foundation. To avoid the maintenance complexity and potential
| performance impact of adding kernel code for implementor-specific
| RISC-V extensions, we'll only consider patches for extensions that either:
|
| - Have been officially frozen or ratified by the RISC-V Foundation, or
| - Have been implemented in hardware that is widely available, per standard
| Linux practice.
The xventanacondops bits don't qualify under the first entry, and I
don't think they qualify under the second yet. Am I wrong?
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next prev parent reply other threads:[~2023-09-25 15:36 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-25 13:38 [PATCH v2 0/9] KVM RISC-V Conditional Operations Anup Patel
2023-09-25 13:38 ` [PATCH v2 1/9] dt-bindings: riscv: Add XVentanaCondOps extension entry Anup Patel
2023-09-25 14:11 ` Andrew Jones
2023-09-25 13:38 ` [PATCH v2 2/9] RISC-V: Detect XVentanaCondOps from ISA string Anup Patel
2023-09-25 17:48 ` Charlie Jenkins
2023-09-25 18:12 ` Charlie Jenkins
2023-09-26 4:08 ` Anup Patel
2023-09-26 4:14 ` Anup Patel
2023-09-27 2:13 ` Charlie Jenkins
2023-09-25 13:38 ` [PATCH v2 3/9] dt-bindings: riscv: Add Zicond extension entry Anup Patel
2023-09-25 14:12 ` Andrew Jones
2023-09-25 13:38 ` [PATCH v2 4/9] RISC-V: Detect Zicond from ISA string Anup Patel
2023-09-25 14:13 ` Andrew Jones
2023-09-25 13:38 ` [PATCH v2 5/9] RISC-V: KVM: Allow XVentanaCondOps extension for Guest/VM Anup Patel
2023-09-25 13:38 ` [PATCH v2 6/9] RISC-V: KVM: Allow Zicond " Anup Patel
2023-09-25 13:38 ` [PATCH v2 7/9] KVM: riscv: selftests: Add senvcfg register to get-reg-list test Anup Patel
2023-09-25 13:38 ` [PATCH v2 8/9] KVM: riscv: selftests: Add smstateen registers " Anup Patel
2023-09-25 13:38 ` [PATCH v2 9/9] KVM: riscv: selftests: Add condops extensions " Anup Patel
2023-09-25 14:16 ` Andrew Jones
2023-09-25 15:33 ` [PATCH v2 0/9] KVM RISC-V Conditional Operations Conor Dooley
2023-09-25 15:36 ` Conor Dooley [this message]
2023-09-27 14:24 ` Anup Patel
2023-09-27 14:45 ` Conor Dooley
2023-09-27 15:01 ` Palmer Dabbelt
2023-09-27 15:26 ` Anup Patel
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