From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andrew Jones Date: Mon, 15 Apr 2024 15:01:42 +0200 Subject: [PATCH v6 01/24] RISC-V: Fix the typo in Scountovf CSR name In-Reply-To: <20240411000752.955910-2-atishp@rivosinc.com> References: <20240411000752.955910-1-atishp@rivosinc.com> <20240411000752.955910-2-atishp@rivosinc.com> Message-ID: <20240415-b899e62329c901f59db9f146@orel> List-Id: To: kvm-riscv@lists.infradead.org MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit On Wed, Apr 10, 2024 at 05:07:29PM -0700, Atish Patra wrote: > The counter overflow CSR name is "scountovf" not "sscountovf". > > Fix the csr name. > > Fixes: 4905ec2fb7e6 ("RISC-V: Add sscofpmf extension support") > Reviewed-by: Cl?ment L?ger > Reviewed-by: Conor Dooley > Reviewed-by: Anup Patel > Signed-off-by: Atish Patra > --- > arch/riscv/include/asm/csr.h | 2 +- > drivers/perf/riscv_pmu_sbi.c | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h > index 2468c55933cd..9d1b07932794 100644 > --- a/arch/riscv/include/asm/csr.h > +++ b/arch/riscv/include/asm/csr.h > @@ -281,7 +281,7 @@ > #define CSR_HPMCOUNTER30H 0xc9e > #define CSR_HPMCOUNTER31H 0xc9f > > -#define CSR_SSCOUNTOVF 0xda0 > +#define CSR_SCOUNTOVF 0xda0 > > #define CSR_SSTATUS 0x100 > #define CSR_SIE 0x104 > diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c > index 8cbe6e5f9c39..3e44d2fb8bf8 100644 > --- a/drivers/perf/riscv_pmu_sbi.c > +++ b/drivers/perf/riscv_pmu_sbi.c > @@ -27,7 +27,7 @@ > > #define ALT_SBI_PMU_OVERFLOW(__ovl) \ > asm volatile(ALTERNATIVE_2( \ > - "csrr %0, " __stringify(CSR_SSCOUNTOVF), \ > + "csrr %0, " __stringify(CSR_SCOUNTOVF), \ > "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF), \ > THEAD_VENDOR_ID, ERRATA_THEAD_PMU, \ > CONFIG_ERRATA_THEAD_PMU, \ > -- > 2.34.1 > Reviewed-by: Andrew Jones