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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a1c832a90sm47386140f8f.28.2025.01.06.05.55.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jan 2025 05:55:13 -0800 (PST) Date: Mon, 6 Jan 2025 14:55:12 +0100 From: Andrew Jones To: =?utf-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= Cc: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Anup Patel , Atish Patra Subject: Re: [kvm-unit-tests PATCH v4 0/5] riscv: add SBI SSE extension tests Message-ID: <20250106-daa8e0da7de4e560f17b4d38@orel> References: <20241125162200.1630845-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250106_055516_210385_77198BBA X-CRM114-Status: GOOD ( 19.05 ) X-BeenThere: kvm-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "kvm-riscv" Errors-To: kvm-riscv-bounces+kvm-riscv=archiver.kernel.org@lists.infradead.org On Mon, Jan 06, 2025 at 11:11:42AM +0100, Cl=E9ment L=E9ger wrote: > Gentle ping ? Thanks for the reminder. I'll try to get to it this week. drew > = > Thanks, > = > Cl=E9ment > = > On 25/11/2024 17:21, Cl=E9ment L=E9ger wrote: > > This series adds an individual test for SBI SSE extension as well as > > needed infrastructure for SSE support. It also adds test specific > > asm-offsets generation to use custom OFFSET and DEFINE from the test > > directory. > > = > > --- > > = > > V4: > > - Fix typo sbi_ext_ss_fid -> sbi_ext_sse_fid > > - Add proper asm-offset generation for tests > > - Move SSE specific file from lib/riscv to riscv/ > > = > > V3: > > - Add -deps variable for test specific dependencies > > - Fix formatting errors/typo in sbi.h > > - Add missing double trap event > > - Alphabetize sbi-sse.c includes > > - Fix a6 content after unmasking event > > - Add SSE HART_MASK/UNMASK test > > - Use mv instead of move > > - move sbi_check_sse() definition in sbi.c > > - Remove sbi_sse test from unitests.cfg > > = > > V2: > > - Rebased on origin/master and integrate it into sbi.c tests > > = > > Cl=E9ment L=E9ger (5): > > kbuild: allow multiple asm-offsets file to be generated > > riscv: use asm-offsets to generate SBI_EXT_HSM values > > riscv: Add "-deps" handling for tests > > riscv: lib: Add SBI SSE extension definitions > > riscv: sbi: Add SSE extension tests > > = > > scripts/asm-offsets.mak | 22 +- > > riscv/Makefile | 10 +- > > lib/riscv/asm/csr.h | 2 + > > lib/riscv/asm/sbi.h | 83 +++ > > riscv/sbi-tests.h | 12 + > > riscv/sbi-asm.S | 96 +++- > > riscv/asm-offsets-test.c | 19 + > > riscv/sbi-sse.c | 1043 ++++++++++++++++++++++++++++++++++++++ > > riscv/sbi.c | 3 + > > riscv/.gitignore | 1 + > > 10 files changed, 1278 insertions(+), 13 deletions(-) > > create mode 100644 riscv/asm-offsets-test.c > > create mode 100644 riscv/sbi-sse.c > > create mode 100644 riscv/.gitignore > > = > = -- = kvm-riscv mailing list kvm-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/kvm-riscv