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([111.94.32.24]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29eea016c6esm85494715ad.59.2025.12.13.07.09.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Dec 2025 07:09:11 -0800 (PST) From: James Raphael Tiovalen To: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Cc: andrew.jones@linux.dev, atishp@rivosinc.com, James Raphael Tiovalen Subject: [kvm-unit-tests PATCH 2/4] lib: riscv: Add SBI PMU support Date: Sat, 13 Dec 2025 23:08:46 +0800 Message-ID: <20251213150848.149729-3-jamestiotio@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251213150848.149729-1-jamestiotio@gmail.com> References: <20251213150848.149729-1-jamestiotio@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251213_070912_882930_EA14197D X-CRM114-Status: UNSURE ( 7.92 ) X-CRM114-Notice: Please train this message. X-BeenThere: kvm-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "kvm-riscv" Errors-To: kvm-riscv-bounces+kvm-riscv=archiver.kernel.org@lists.infradead.org Add support for all of the SBI PMU functions, which will be used by the SBI tests. Signed-off-by: James Raphael Tiovalen --- lib/riscv/asm/sbi.h | 22 ++++++++++++++ lib/riscv/sbi.c | 73 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 95 insertions(+) diff --git a/lib/riscv/asm/sbi.h b/lib/riscv/asm/sbi.h index 35dbf508..8794c126 100644 --- a/lib/riscv/asm/sbi.h +++ b/lib/riscv/asm/sbi.h @@ -390,5 +390,27 @@ struct sbiret sbi_fwft_set(uint32_t feature, unsigned long value, unsigned long struct sbiret sbi_fwft_get_raw(unsigned long feature); struct sbiret sbi_fwft_get(uint32_t feature); +struct sbiret sbi_pmu_num_counters(void); +struct sbiret sbi_pmu_counter_get_info(unsigned long counter_idx); +struct sbiret sbi_pmu_counter_config_matching(unsigned long counter_idx_base, + unsigned long counter_idx_mask, + unsigned long config_flags, + unsigned long event_idx, + unsigned long event_data); +struct sbiret sbi_pmu_counter_start(unsigned long counter_idx_base, unsigned long counter_idx_mask, + unsigned long start_flags, unsigned long initial_value); +struct sbiret sbi_pmu_counter_stop(unsigned long counter_idx_base, unsigned long counter_idx_mask, + unsigned long stop_flags); +struct sbiret sbi_pmu_counter_fw_read(unsigned long counter_idx); +struct sbiret sbi_pmu_counter_fw_read_hi(unsigned long counter_idx); +struct sbiret sbi_pmu_snapshot_set_shmem_raw(unsigned long shmem_phys_lo, + unsigned long shmem_phys_hi, + unsigned long flags); +struct sbiret sbi_pmu_snapshot_set_shmem(unsigned long *shmem, unsigned long flags); +struct sbiret sbi_pmu_event_get_info_raw(unsigned long shmem_phys_lo, unsigned long shmem_phys_hi, + unsigned long num_entries, unsigned long flags); +struct sbiret sbi_pmu_event_get_info(unsigned long *shmem, unsigned long num_entries, + unsigned long flags); + #endif /* !__ASSEMBLER__ */ #endif /* _ASMRISCV_SBI_H_ */ diff --git a/lib/riscv/sbi.c b/lib/riscv/sbi.c index 39f6138f..ca8f3d33 100644 --- a/lib/riscv/sbi.c +++ b/lib/riscv/sbi.c @@ -32,6 +32,79 @@ struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0, return ret; } +struct sbiret sbi_pmu_num_counters(void) +{ + return sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_NUM_COUNTERS, 0, 0, 0, 0, 0, 0); +} + +struct sbiret sbi_pmu_counter_get_info(unsigned long counter_idx) +{ + return sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_GET_INFO, counter_idx, 0, 0, 0, 0, 0); +} + +struct sbiret sbi_pmu_counter_config_matching(unsigned long counter_idx_base, + unsigned long counter_idx_mask, + unsigned long config_flags, + unsigned long event_idx, + unsigned long event_data) +{ + return sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CONFIG_MATCHING, counter_idx_base, + counter_idx_mask, config_flags, event_idx, event_data, 0); +} + +struct sbiret sbi_pmu_counter_start(unsigned long counter_idx_base, unsigned long counter_idx_mask, + unsigned long start_flags, unsigned long initial_value) +{ + return sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, counter_idx_base, + counter_idx_mask, start_flags, initial_value, 0, 0); +} + +struct sbiret sbi_pmu_counter_stop(unsigned long counter_idx_base, unsigned long counter_idx_mask, + unsigned long stop_flags) +{ + return sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP, counter_idx_base, + counter_idx_mask, stop_flags, 0, 0, 0); +} + +struct sbiret sbi_pmu_counter_fw_read(unsigned long counter_idx) +{ + return sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_FW_READ, counter_idx, 0, 0, 0, 0, 0); +} + +struct sbiret sbi_pmu_counter_fw_read_hi(unsigned long counter_idx) +{ + return sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_FW_READ_HI, counter_idx, 0, 0, 0, 0, 0); +} + +struct sbiret sbi_pmu_snapshot_set_shmem_raw(unsigned long shmem_phys_lo, unsigned long shmem_phys_hi, + unsigned long flags) +{ + return sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_SNAPSHOT_SET_SHMEM, shmem_phys_lo, + shmem_phys_hi, flags, 0, 0, 0); +} + +struct sbiret sbi_pmu_snapshot_set_shmem(unsigned long *shmem, unsigned long flags) +{ + phys_addr_t p = virt_to_phys(shmem); + + return sbi_pmu_snapshot_set_shmem_raw(lower_32_bits(p), upper_32_bits(p), flags); +} + +struct sbiret sbi_pmu_event_get_info_raw(unsigned long shmem_phys_lo, unsigned long shmem_phys_hi, + unsigned long num_entries, unsigned long flags) +{ + return sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_EVENT_GET_INFO, shmem_phys_lo, + shmem_phys_hi, num_entries, flags, 0, 0); +} + +struct sbiret sbi_pmu_event_get_info(unsigned long *shmem, unsigned long num_entries, + unsigned long flags) +{ + phys_addr_t p = virt_to_phys(shmem); + + return sbi_pmu_event_get_info_raw(lower_32_bits(p), upper_32_bits(p), num_entries, flags); +} + struct sbiret sbi_sse_read_attrs_raw(unsigned long event_id, unsigned long base_attr_id, unsigned long attr_count, unsigned long phys_lo, unsigned long phys_hi) -- 2.43.0 -- kvm-riscv mailing list kvm-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/kvm-riscv