* [PATCH v4 01/10] riscv: Add ISA extension parsing for Zalasr
2025-10-20 4:20 [PATCH v4 00/10] riscv: Add Zalasr ISA extension support Xu Lu
@ 2025-10-20 4:20 ` Xu Lu
2025-10-20 4:20 ` [PATCH v4 02/10] dt-bindings: riscv: Add Zalasr ISA extension description Xu Lu
` (5 subsequent siblings)
6 siblings, 0 replies; 13+ messages in thread
From: Xu Lu @ 2025-10-20 4:20 UTC (permalink / raw)
To: corbet, paul.walmsley, palmer, aou, alex, robh, krzk+dt, conor+dt,
will, peterz, boqun.feng, mark.rutland, anup, atish.patra,
pbonzini, shuah, parri.andrea, ajones, brs, guoren
Cc: linux-doc, linux-riscv, linux-kernel, devicetree, kvm, kvm-riscv,
linux-kselftest, apw, joe, lukas.bulwahn, Xu Lu
Add parsing for Zalasr ISA extension.
Signed-off-by: Xu Lu <luxu.kernel@bytedance.com>
---
arch/riscv/include/asm/hwcap.h | 1 +
arch/riscv/kernel/cpufeature.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index affd63e11b0a3..ae3852c4f2ca2 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -106,6 +106,7 @@
#define RISCV_ISA_EXT_ZAAMO 97
#define RISCV_ISA_EXT_ZALRSC 98
#define RISCV_ISA_EXT_ZICBOP 99
+#define RISCV_ISA_EXT_ZALASR 100
#define RISCV_ISA_EXT_XLINUXENVCFG 127
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 743d53415572e..bf9d3d92bf372 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -472,6 +472,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
__RISCV_ISA_EXT_DATA(zaamo, RISCV_ISA_EXT_ZAAMO),
__RISCV_ISA_EXT_DATA(zabha, RISCV_ISA_EXT_ZABHA),
__RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS),
+ __RISCV_ISA_EXT_DATA(zalasr, RISCV_ISA_EXT_ZALASR),
__RISCV_ISA_EXT_DATA(zalrsc, RISCV_ISA_EXT_ZALRSC),
__RISCV_ISA_EXT_DATA(zawrs, RISCV_ISA_EXT_ZAWRS),
__RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA),
--
2.20.1
--
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^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v4 02/10] dt-bindings: riscv: Add Zalasr ISA extension description
2025-10-20 4:20 [PATCH v4 00/10] riscv: Add Zalasr ISA extension support Xu Lu
2025-10-20 4:20 ` [PATCH v4 01/10] riscv: Add ISA extension parsing for Zalasr Xu Lu
@ 2025-10-20 4:20 ` Xu Lu
2025-10-20 17:21 ` Conor Dooley
2025-10-20 4:20 ` [PATCH v4 03/10] riscv: hwprobe: Export Zalasr extension Xu Lu
` (4 subsequent siblings)
6 siblings, 1 reply; 13+ messages in thread
From: Xu Lu @ 2025-10-20 4:20 UTC (permalink / raw)
To: corbet, paul.walmsley, palmer, aou, alex, robh, krzk+dt, conor+dt,
will, peterz, boqun.feng, mark.rutland, anup, atish.patra,
pbonzini, shuah, parri.andrea, ajones, brs, guoren
Cc: linux-doc, linux-riscv, linux-kernel, devicetree, kvm, kvm-riscv,
linux-kselftest, apw, joe, lukas.bulwahn, Xu Lu
Add description for the Zalasr ISA extension
Signed-off-by: Xu Lu <luxu.kernel@bytedance.com>
---
Documentation/devicetree/bindings/riscv/extensions.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index ede6a58ccf534..100fe53fb0731 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -242,6 +242,11 @@ properties:
is supported as ratified at commit 5059e0ca641c ("update to
ratified") of the riscv-zacas.
+ - const: zalasr
+ description: |
+ The standard Zalasr extension for load-acquire/store-release as frozen
+ at commit 194f0094 ("Version 0.9 for freeze") of riscv-zalasr.
+
- const: zalrsc
description: |
The standard Zalrsc extension for load-reserved/store-conditional as
--
2.20.1
--
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^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v4 02/10] dt-bindings: riscv: Add Zalasr ISA extension description
2025-10-20 4:20 ` [PATCH v4 02/10] dt-bindings: riscv: Add Zalasr ISA extension description Xu Lu
@ 2025-10-20 17:21 ` Conor Dooley
0 siblings, 0 replies; 13+ messages in thread
From: Conor Dooley @ 2025-10-20 17:21 UTC (permalink / raw)
To: Xu Lu
Cc: corbet, paul.walmsley, palmer, aou, alex, robh, krzk+dt, conor+dt,
will, peterz, boqun.feng, mark.rutland, anup, atish.patra,
pbonzini, shuah, parri.andrea, ajones, brs, guoren, linux-doc,
linux-riscv, linux-kernel, devicetree, kvm, kvm-riscv,
linux-kselftest, apw, joe, lukas.bulwahn
[-- Attachment #1.1: Type: text/plain, Size: 75 bytes --]
Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
[-- Attachment #2: Type: text/plain, Size: 111 bytes --]
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^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v4 03/10] riscv: hwprobe: Export Zalasr extension
2025-10-20 4:20 [PATCH v4 00/10] riscv: Add Zalasr ISA extension support Xu Lu
2025-10-20 4:20 ` [PATCH v4 01/10] riscv: Add ISA extension parsing for Zalasr Xu Lu
2025-10-20 4:20 ` [PATCH v4 02/10] dt-bindings: riscv: Add Zalasr ISA extension description Xu Lu
@ 2025-10-20 4:20 ` Xu Lu
2025-10-20 13:46 ` Guo Ren
2025-10-20 4:20 ` [PATCH v4 04/10] riscv: Introduce Zalasr instructions Xu Lu
` (3 subsequent siblings)
6 siblings, 1 reply; 13+ messages in thread
From: Xu Lu @ 2025-10-20 4:20 UTC (permalink / raw)
To: corbet, paul.walmsley, palmer, aou, alex, robh, krzk+dt, conor+dt,
will, peterz, boqun.feng, mark.rutland, anup, atish.patra,
pbonzini, shuah, parri.andrea, ajones, brs, guoren
Cc: linux-doc, linux-riscv, linux-kernel, devicetree, kvm, kvm-riscv,
linux-kselftest, apw, joe, lukas.bulwahn, Xu Lu
Export the Zalasr extension to userspace using hwprobe.
Signed-off-by: Xu Lu <luxu.kernel@bytedance.com>
---
Documentation/arch/riscv/hwprobe.rst | 5 ++++-
arch/riscv/include/uapi/asm/hwprobe.h | 1 +
arch/riscv/kernel/sys_hwprobe.c | 1 +
3 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
index 2aa9be272d5de..067a3595fb9d5 100644
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@ -249,6 +249,9 @@ The following keys are defined:
defined in the in the RISC-V ISA manual starting from commit e87412e621f1
("integrate Zaamo and Zalrsc text (#1304)").
+ * :c:macro:`RISCV_HWPROBE_EXT_ZALASR`: The Zalasr extension is supported as
+ frozen at commit 194f0094 ("Version 0.9 for freeze") of riscv-zalasr.
+
* :c:macro:`RISCV_HWPROBE_EXT_ZALRSC`: The Zalrsc extension is supported as
defined in the in the RISC-V ISA manual starting from commit e87412e621f1
("integrate Zaamo and Zalrsc text (#1304)").
@@ -360,4 +363,4 @@ The following keys are defined:
* :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVFWMACCQQQ`: The Xsfvfwmaccqqq
vendor extension is supported in version 1.0 of Matrix Multiply Accumulate
- Instruction Extensions Specification.
\ No newline at end of file
+ Instruction Extensions Specification.
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index aaf6ad9704993..d3a65f8ff7da4 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -82,6 +82,7 @@ struct riscv_hwprobe {
#define RISCV_HWPROBE_EXT_ZAAMO (1ULL << 56)
#define RISCV_HWPROBE_EXT_ZALRSC (1ULL << 57)
#define RISCV_HWPROBE_EXT_ZABHA (1ULL << 58)
+#define RISCV_HWPROBE_EXT_ZALASR (1ULL << 59)
#define RISCV_HWPROBE_KEY_CPUPERF_0 5
#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
#define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
index 0b170e18a2beb..0529e692b1173 100644
--- a/arch/riscv/kernel/sys_hwprobe.c
+++ b/arch/riscv/kernel/sys_hwprobe.c
@@ -99,6 +99,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
EXT_KEY(ZAAMO);
EXT_KEY(ZABHA);
EXT_KEY(ZACAS);
+ EXT_KEY(ZALASR);
EXT_KEY(ZALRSC);
EXT_KEY(ZAWRS);
EXT_KEY(ZBA);
--
2.20.1
--
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^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v4 03/10] riscv: hwprobe: Export Zalasr extension
2025-10-20 4:20 ` [PATCH v4 03/10] riscv: hwprobe: Export Zalasr extension Xu Lu
@ 2025-10-20 13:46 ` Guo Ren
0 siblings, 0 replies; 13+ messages in thread
From: Guo Ren @ 2025-10-20 13:46 UTC (permalink / raw)
To: Xu Lu
Cc: corbet, paul.walmsley, palmer, aou, alex, robh, krzk+dt, conor+dt,
will, peterz, boqun.feng, mark.rutland, anup, atish.patra,
pbonzini, shuah, parri.andrea, ajones, brs, linux-doc,
linux-riscv, linux-kernel, devicetree, kvm, kvm-riscv,
linux-kselftest, apw, joe, lukas.bulwahn
On Mon, Oct 20, 2025 at 12:21 PM Xu Lu <luxu.kernel@bytedance.com> wrote:
>
> Export the Zalasr extension to userspace using hwprobe.
>
> Signed-off-by: Xu Lu <luxu.kernel@bytedance.com>
> ---
> Documentation/arch/riscv/hwprobe.rst | 5 ++++-
> arch/riscv/include/uapi/asm/hwprobe.h | 1 +
> arch/riscv/kernel/sys_hwprobe.c | 1 +
> 3 files changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
> index 2aa9be272d5de..067a3595fb9d5 100644
> --- a/Documentation/arch/riscv/hwprobe.rst
> +++ b/Documentation/arch/riscv/hwprobe.rst
> @@ -249,6 +249,9 @@ The following keys are defined:
> defined in the in the RISC-V ISA manual starting from commit e87412e621f1
> ("integrate Zaamo and Zalrsc text (#1304)").
>
> + * :c:macro:`RISCV_HWPROBE_EXT_ZALASR`: The Zalasr extension is supported as
> + frozen at commit 194f0094 ("Version 0.9 for freeze") of riscv-zalasr.
"Frozen Version 0.9" might not be proper; it denotes the current
temporary state, not the goal of the patch.
> +
> * :c:macro:`RISCV_HWPROBE_EXT_ZALRSC`: The Zalrsc extension is supported as
> defined in the in the RISC-V ISA manual starting from commit e87412e621f1
> ("integrate Zaamo and Zalrsc text (#1304)").
> @@ -360,4 +363,4 @@ The following keys are defined:
>
> * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVFWMACCQQQ`: The Xsfvfwmaccqqq
> vendor extension is supported in version 1.0 of Matrix Multiply Accumulate
> - Instruction Extensions Specification.
> \ No newline at end of file
> + Instruction Extensions Specification.
> diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
> index aaf6ad9704993..d3a65f8ff7da4 100644
> --- a/arch/riscv/include/uapi/asm/hwprobe.h
> +++ b/arch/riscv/include/uapi/asm/hwprobe.h
> @@ -82,6 +82,7 @@ struct riscv_hwprobe {
> #define RISCV_HWPROBE_EXT_ZAAMO (1ULL << 56)
> #define RISCV_HWPROBE_EXT_ZALRSC (1ULL << 57)
> #define RISCV_HWPROBE_EXT_ZABHA (1ULL << 58)
> +#define RISCV_HWPROBE_EXT_ZALASR (1ULL << 59)
> #define RISCV_HWPROBE_KEY_CPUPERF_0 5
> #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
> #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
> diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
> index 0b170e18a2beb..0529e692b1173 100644
> --- a/arch/riscv/kernel/sys_hwprobe.c
> +++ b/arch/riscv/kernel/sys_hwprobe.c
> @@ -99,6 +99,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
> EXT_KEY(ZAAMO);
> EXT_KEY(ZABHA);
> EXT_KEY(ZACAS);
> + EXT_KEY(ZALASR);
> EXT_KEY(ZALRSC);
> EXT_KEY(ZAWRS);
> EXT_KEY(ZBA);
> --
> 2.20.1
>
--
Best Regards
Guo Ren
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^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v4 04/10] riscv: Introduce Zalasr instructions
2025-10-20 4:20 [PATCH v4 00/10] riscv: Add Zalasr ISA extension support Xu Lu
` (2 preceding siblings ...)
2025-10-20 4:20 ` [PATCH v4 03/10] riscv: hwprobe: Export Zalasr extension Xu Lu
@ 2025-10-20 4:20 ` Xu Lu
2025-10-20 13:34 ` Guo Ren
2025-10-20 4:34 ` [PATCH v4 00/10] riscv: Add Zalasr ISA extension support Xu Lu
` (2 subsequent siblings)
6 siblings, 1 reply; 13+ messages in thread
From: Xu Lu @ 2025-10-20 4:20 UTC (permalink / raw)
To: corbet, paul.walmsley, palmer, aou, alex, robh, krzk+dt, conor+dt,
will, peterz, boqun.feng, mark.rutland, anup, atish.patra,
pbonzini, shuah, parri.andrea, ajones, brs, guoren
Cc: linux-doc, linux-riscv, linux-kernel, devicetree, kvm, kvm-riscv,
linux-kselftest, apw, joe, lukas.bulwahn, Xu Lu
Introduce l{b|h|w|d}.{aq|aqrl} and s{b|h|w|d}.{rl|aqrl} instruction
encodings.
Signed-off-by: Xu Lu <luxu.kernel@bytedance.com>
---
arch/riscv/include/asm/insn-def.h | 79 +++++++++++++++++++++++++++++++
1 file changed, 79 insertions(+)
diff --git a/arch/riscv/include/asm/insn-def.h b/arch/riscv/include/asm/insn-def.h
index d5adbaec1d010..3fec7e66ce50f 100644
--- a/arch/riscv/include/asm/insn-def.h
+++ b/arch/riscv/include/asm/insn-def.h
@@ -179,6 +179,7 @@
#define RV___RS1(v) __RV_REG(v)
#define RV___RS2(v) __RV_REG(v)
+#define RV_OPCODE_AMO RV_OPCODE(47)
#define RV_OPCODE_MISC_MEM RV_OPCODE(15)
#define RV_OPCODE_OP_IMM RV_OPCODE(19)
#define RV_OPCODE_SYSTEM RV_OPCODE(115)
@@ -208,6 +209,84 @@
__ASM_STR(.error "hlv.d requires 64-bit support")
#endif
+#define LB_AQ(dest, addr) \
+ INSN_R(OPCODE_AMO, FUNC3(0), FUNC7(26), \
+ RD(dest), RS1(addr), __RS2(0))
+
+#define LB_AQRL(dest, addr) \
+ INSN_R(OPCODE_AMO, FUNC3(0), FUNC7(27), \
+ RD(dest), RS1(addr), __RS2(0))
+
+#define LH_AQ(dest, addr) \
+ INSN_R(OPCODE_AMO, FUNC3(1), FUNC7(26), \
+ RD(dest), RS1(addr), __RS2(0))
+
+#define LH_AQRL(dest, addr) \
+ INSN_R(OPCODE_AMO, FUNC3(1), FUNC7(27), \
+ RD(dest), RS1(addr), __RS2(0))
+
+#define LW_AQ(dest, addr) \
+ INSN_R(OPCODE_AMO, FUNC3(2), FUNC7(26), \
+ RD(dest), RS1(addr), __RS2(0))
+
+#define LW_AQRL(dest, addr) \
+ INSN_R(OPCODE_AMO, FUNC3(2), FUNC7(27), \
+ RD(dest), RS1(addr), __RS2(0))
+
+#define SB_RL(src, addr) \
+ INSN_R(OPCODE_AMO, FUNC3(0), FUNC7(29), \
+ __RD(0), RS1(addr), RS2(src))
+
+#define SB_AQRL(src, addr) \
+ INSN_R(OPCODE_AMO, FUNC3(0), FUNC7(31), \
+ __RD(0), RS1(addr), RS2(src))
+
+#define SH_RL(src, addr) \
+ INSN_R(OPCODE_AMO, FUNC3(1), FUNC7(29), \
+ __RD(0), RS1(addr), RS2(src))
+
+#define SH_AQRL(src, addr) \
+ INSN_R(OPCODE_AMO, FUNC3(1), FUNC7(31), \
+ __RD(0), RS1(addr), RS2(src))
+
+#define SW_RL(src, addr) \
+ INSN_R(OPCODE_AMO, FUNC3(2), FUNC7(29), \
+ __RD(0), RS1(addr), RS2(src))
+
+#define SW_AQRL(src, addr) \
+ INSN_R(OPCODE_AMO, FUNC3(2), FUNC7(31), \
+ __RD(0), RS1(addr), RS2(src))
+
+#ifdef CONFIG_64BIT
+#define LD_AQ(dest, addr) \
+ INSN_R(OPCODE_AMO, FUNC3(3), FUNC7(26), \
+ RD(dest), RS1(addr), __RS2(0))
+
+#define LD_AQRL(dest, addr) \
+ INSN_R(OPCODE_AMO, FUNC3(3), FUNC7(27), \
+ RD(dest), RS1(addr), __RS2(0))
+
+#define SD_RL(src, addr) \
+ INSN_R(OPCODE_AMO, FUNC3(3), FUNC7(29), \
+ __RD(0), RS1(addr), RS2(src))
+
+#define SD_AQRL(src, addr) \
+ INSN_R(OPCODE_AMO, FUNC3(3), FUNC7(31), \
+ __RD(0), RS1(addr), RS2(src))
+#else
+#define LD_AQ(dest, addr) \
+ __ASM_STR(.error "ld.aq requires 64-bit support")
+
+#define LD_AQRL(dest, addr) \
+ __ASM_STR(.error "ld.aqrl requires 64-bit support")
+
+#define SD_RL(dest, addr) \
+ __ASM_STR(.error "sd.rl requires 64-bit support")
+
+#define SD_AQRL(dest, addr) \
+ __ASM_STR(.error "sd.aqrl requires 64-bit support")
+#endif
+
#define SINVAL_VMA(vaddr, asid) \
INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(11), \
__RD(0), RS1(vaddr), RS2(asid))
--
2.20.1
--
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^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v4 04/10] riscv: Introduce Zalasr instructions
2025-10-20 4:20 ` [PATCH v4 04/10] riscv: Introduce Zalasr instructions Xu Lu
@ 2025-10-20 13:34 ` Guo Ren
0 siblings, 0 replies; 13+ messages in thread
From: Guo Ren @ 2025-10-20 13:34 UTC (permalink / raw)
To: Xu Lu
Cc: corbet, paul.walmsley, palmer, aou, alex, robh, krzk+dt, conor+dt,
will, peterz, boqun.feng, mark.rutland, anup, atish.patra,
pbonzini, shuah, parri.andrea, ajones, brs, linux-doc,
linux-riscv, linux-kernel, devicetree, kvm, kvm-riscv,
linux-kselftest, apw, joe, lukas.bulwahn
On Mon, Oct 20, 2025 at 12:21 PM Xu Lu <luxu.kernel@bytedance.com> wrote:
>
> Introduce l{b|h|w|d}.{aq|aqrl} and s{b|h|w|d}.{rl|aqrl} instruction
> encodings.
>
> Signed-off-by: Xu Lu <luxu.kernel@bytedance.com>
> ---
> arch/riscv/include/asm/insn-def.h | 79 +++++++++++++++++++++++++++++++
> 1 file changed, 79 insertions(+)
>
> diff --git a/arch/riscv/include/asm/insn-def.h b/arch/riscv/include/asm/insn-def.h
> index d5adbaec1d010..3fec7e66ce50f 100644
> --- a/arch/riscv/include/asm/insn-def.h
> +++ b/arch/riscv/include/asm/insn-def.h
> @@ -179,6 +179,7 @@
> #define RV___RS1(v) __RV_REG(v)
> #define RV___RS2(v) __RV_REG(v)
>
> +#define RV_OPCODE_AMO RV_OPCODE(47)
> #define RV_OPCODE_MISC_MEM RV_OPCODE(15)
> #define RV_OPCODE_OP_IMM RV_OPCODE(19)
> #define RV_OPCODE_SYSTEM RV_OPCODE(115)
> @@ -208,6 +209,84 @@
> __ASM_STR(.error "hlv.d requires 64-bit support")
> #endif
>
> +#define LB_AQ(dest, addr) \
> + INSN_R(OPCODE_AMO, FUNC3(0), FUNC7(26), \
> + RD(dest), RS1(addr), __RS2(0))
> +
> +#define LB_AQRL(dest, addr) \
> + INSN_R(OPCODE_AMO, FUNC3(0), FUNC7(27), \
> + RD(dest), RS1(addr), __RS2(0))
> +
> +#define LH_AQ(dest, addr) \
> + INSN_R(OPCODE_AMO, FUNC3(1), FUNC7(26), \
> + RD(dest), RS1(addr), __RS2(0))
> +
> +#define LH_AQRL(dest, addr) \
> + INSN_R(OPCODE_AMO, FUNC3(1), FUNC7(27), \
> + RD(dest), RS1(addr), __RS2(0))
> +
> +#define LW_AQ(dest, addr) \
> + INSN_R(OPCODE_AMO, FUNC3(2), FUNC7(26), \
> + RD(dest), RS1(addr), __RS2(0))
> +
> +#define LW_AQRL(dest, addr) \
> + INSN_R(OPCODE_AMO, FUNC3(2), FUNC7(27), \
> + RD(dest), RS1(addr), __RS2(0))
> +
> +#define SB_RL(src, addr) \
> + INSN_R(OPCODE_AMO, FUNC3(0), FUNC7(29), \
> + __RD(0), RS1(addr), RS2(src))
> +
> +#define SB_AQRL(src, addr) \
> + INSN_R(OPCODE_AMO, FUNC3(0), FUNC7(31), \
> + __RD(0), RS1(addr), RS2(src))
> +
> +#define SH_RL(src, addr) \
> + INSN_R(OPCODE_AMO, FUNC3(1), FUNC7(29), \
> + __RD(0), RS1(addr), RS2(src))
> +
> +#define SH_AQRL(src, addr) \
> + INSN_R(OPCODE_AMO, FUNC3(1), FUNC7(31), \
> + __RD(0), RS1(addr), RS2(src))
> +
> +#define SW_RL(src, addr) \
> + INSN_R(OPCODE_AMO, FUNC3(2), FUNC7(29), \
> + __RD(0), RS1(addr), RS2(src))
> +
> +#define SW_AQRL(src, addr) \
> + INSN_R(OPCODE_AMO, FUNC3(2), FUNC7(31), \
> + __RD(0), RS1(addr), RS2(src))
> +
> +#ifdef CONFIG_64BIT
> +#define LD_AQ(dest, addr) \
> + INSN_R(OPCODE_AMO, FUNC3(3), FUNC7(26), \
> + RD(dest), RS1(addr), __RS2(0))
> +
> +#define LD_AQRL(dest, addr) \
> + INSN_R(OPCODE_AMO, FUNC3(3), FUNC7(27), \
> + RD(dest), RS1(addr), __RS2(0))
> +
> +#define SD_RL(src, addr) \
> + INSN_R(OPCODE_AMO, FUNC3(3), FUNC7(29), \
> + __RD(0), RS1(addr), RS2(src))
> +
> +#define SD_AQRL(src, addr) \
> + INSN_R(OPCODE_AMO, FUNC3(3), FUNC7(31), \
> + __RD(0), RS1(addr), RS2(src))
> +#else
> +#define LD_AQ(dest, addr) \
> + __ASM_STR(.error "ld.aq requires 64-bit support")
> +
> +#define LD_AQRL(dest, addr) \
> + __ASM_STR(.error "ld.aqrl requires 64-bit support")
> +
> +#define SD_RL(dest, addr) \
> + __ASM_STR(.error "sd.rl requires 64-bit support")
> +
> +#define SD_AQRL(dest, addr) \
> + __ASM_STR(.error "sd.aqrl requires 64-bit support")
> +#endif
> +
> #define SINVAL_VMA(vaddr, asid) \
> INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(11), \
> __RD(0), RS1(vaddr), RS2(asid))
> --
> 2.20.1
>
I didn't find problem.
Reviewed-by: Guo Ren <guoren@kernel.org>
--
Best Regards
Guo Ren
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v4 00/10] riscv: Add Zalasr ISA extension support
2025-10-20 4:20 [PATCH v4 00/10] riscv: Add Zalasr ISA extension support Xu Lu
` (3 preceding siblings ...)
2025-10-20 4:20 ` [PATCH v4 04/10] riscv: Introduce Zalasr instructions Xu Lu
@ 2025-10-20 4:34 ` Xu Lu
2025-10-24 21:47 ` Andrea Parri
2025-11-19 12:30 ` patchwork-bot+linux-riscv
6 siblings, 0 replies; 13+ messages in thread
From: Xu Lu @ 2025-10-20 4:34 UTC (permalink / raw)
To: corbet, paul.walmsley, palmer, aou, alex, robh, krzk+dt, conor+dt,
will, peterz, boqun.feng, mark.rutland, anup, atish.patra,
pbonzini, shuah, parri.andrea, ajones, brs, guoren
Cc: linux-doc, linux-riscv, linux-kernel, devicetree, kvm, kvm-riscv,
linux-kselftest, apw, joe, lukas.bulwahn
This series was automatically blocked by Gmail due to too many
recipients, so I resent it twice, causing the emails to appear
discontinuous. I apologize for any inconvenience this may have caused
to the reviewer.
Best regards,
Xu Lu
On Mon, Oct 20, 2025 at 12:21 PM Xu Lu <luxu.kernel@bytedance.com> wrote:
>
> This patch adds support for the Zalasr ISA extension, which supplies the
> real load acquire/store release instructions.
>
> The specification can be found here:
> https://github.com/riscv/riscv-zalasr/blob/main/chapter2.adoc
>
> This patch seires has been tested with ltp on Qemu with Brensan's zalasr
> support patch[1].
>
> Some false positive spacing error happens during patch checking. Thus I
> CCed maintainers of checkpatch.pl as well.
>
> [1] https://lore.kernel.org/all/CAGPSXwJEdtqW=nx71oufZp64nK6tK=0rytVEcz4F-gfvCOXk2w@mail.gmail.com/
>
> v4:
> - Apply acquire/release semantics to arch_atomic operations. Thanks
> to Andrea.
>
> v3:
> - Apply acquire/release semantics to arch_xchg/arch_cmpxchg operations
> so as to ensure FENCE.TSO ordering between operations which precede the
> UNLOCK+LOCK sequence and operations which follow the sequence. Thanks
> to Andrea.
> - Support hwprobe of Zalasr.
> - Allow Zalasr extensions for Guest/VM.
>
> v2:
> - Adjust the order of Zalasr and Zalrsc in dt-bindings. Thanks to
> Conor.
>
> Xu Lu (10):
> riscv: Add ISA extension parsing for Zalasr
> dt-bindings: riscv: Add Zalasr ISA extension description
> riscv: hwprobe: Export Zalasr extension
> riscv: Introduce Zalasr instructions
> riscv: Apply Zalasr to smp_load_acquire/smp_store_release
> riscv: Apply acquire/release semantics to arch_xchg/arch_cmpxchg
> operations
> riscv: Apply acquire/release semantics to arch_atomic operations
> riscv: Remove arch specific __atomic_acquire/release_fence
> RISC-V: KVM: Allow Zalasr extensions for Guest/VM
> RISC-V: KVM: selftests: Add Zalasr extensions to get-reg-list test
>
> Documentation/arch/riscv/hwprobe.rst | 5 +-
> .../devicetree/bindings/riscv/extensions.yaml | 5 +
> arch/riscv/include/asm/atomic.h | 70 ++++++++-
> arch/riscv/include/asm/barrier.h | 91 +++++++++--
> arch/riscv/include/asm/cmpxchg.h | 144 +++++++++---------
> arch/riscv/include/asm/fence.h | 4 -
> arch/riscv/include/asm/hwcap.h | 1 +
> arch/riscv/include/asm/insn-def.h | 79 ++++++++++
> arch/riscv/include/uapi/asm/hwprobe.h | 1 +
> arch/riscv/include/uapi/asm/kvm.h | 1 +
> arch/riscv/kernel/cpufeature.c | 1 +
> arch/riscv/kernel/sys_hwprobe.c | 1 +
> arch/riscv/kvm/vcpu_onereg.c | 2 +
> .../selftests/kvm/riscv/get-reg-list.c | 4 +
> 14 files changed, 314 insertions(+), 95 deletions(-)
>
> --
> 2.20.1
>
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^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH v4 00/10] riscv: Add Zalasr ISA extension support
2025-10-20 4:20 [PATCH v4 00/10] riscv: Add Zalasr ISA extension support Xu Lu
` (4 preceding siblings ...)
2025-10-20 4:34 ` [PATCH v4 00/10] riscv: Add Zalasr ISA extension support Xu Lu
@ 2025-10-24 21:47 ` Andrea Parri
2025-11-19 12:30 ` patchwork-bot+linux-riscv
6 siblings, 0 replies; 13+ messages in thread
From: Andrea Parri @ 2025-10-24 21:47 UTC (permalink / raw)
To: Xu Lu
Cc: corbet, paul.walmsley, palmer, aou, alex, robh, krzk+dt, conor+dt,
will, peterz, boqun.feng, mark.rutland, anup, atish.patra,
pbonzini, shuah, ajones, brs, guoren, linux-doc, linux-riscv,
linux-kernel, devicetree, kvm, kvm-riscv, linux-kselftest, apw,
joe, lukas.bulwahn
On Mon, Oct 20, 2025 at 12:20:46PM +0800, Xu Lu wrote:
> This patch adds support for the Zalasr ISA extension, which supplies the
> real load acquire/store release instructions.
>
> The specification can be found here:
> https://github.com/riscv/riscv-zalasr/blob/main/chapter2.adoc
>
> This patch seires has been tested with ltp on Qemu with Brensan's zalasr
> support patch[1].
>
> Some false positive spacing error happens during patch checking. Thus I
> CCed maintainers of checkpatch.pl as well.
>
> [1] https://lore.kernel.org/all/CAGPSXwJEdtqW=nx71oufZp64nK6tK=0rytVEcz4F-gfvCOXk2w@mail.gmail.com/
>
> v4:
> - Apply acquire/release semantics to arch_atomic operations. Thanks
> to Andrea.
Perhaps I wasn't clear enough, sorry, but I did mean my suggestion
(specifically, the use of .aq/.rl annotations) to be conditional on
zalasr. Same observation for xchg/cmpxchg below. IOW, I really
expected this series to introduce _no changes_ to our lowerings when
!zalasr. If any !zalasr-changes are needed, I'd suggest isolating
/submitting them in dedicated patches.
But other than that, this looks pretty good to me. Perhaps something
else to consider for zalasr is our lowering of smp_cond_load_acquire()
(can't spot an actual bug now, but recall the principle "zalasr -> use
.aq/.rl annotations ..."): riscv currently uses the "generic", fence-
based implementation from include/asm-generic/barrier.h; compare that
with e.g. the implementation from arch/arm64/include/asm/barrier.h .
Andrea
> v3:
> - Apply acquire/release semantics to arch_xchg/arch_cmpxchg operations
> so as to ensure FENCE.TSO ordering between operations which precede the
> UNLOCK+LOCK sequence and operations which follow the sequence. Thanks
> to Andrea.
> - Support hwprobe of Zalasr.
> - Allow Zalasr extensions for Guest/VM.
>
> v2:
> - Adjust the order of Zalasr and Zalrsc in dt-bindings. Thanks to
> Conor.
>
> Xu Lu (10):
> riscv: Add ISA extension parsing for Zalasr
> dt-bindings: riscv: Add Zalasr ISA extension description
> riscv: hwprobe: Export Zalasr extension
> riscv: Introduce Zalasr instructions
> riscv: Apply Zalasr to smp_load_acquire/smp_store_release
> riscv: Apply acquire/release semantics to arch_xchg/arch_cmpxchg
> operations
> riscv: Apply acquire/release semantics to arch_atomic operations
> riscv: Remove arch specific __atomic_acquire/release_fence
> RISC-V: KVM: Allow Zalasr extensions for Guest/VM
> RISC-V: KVM: selftests: Add Zalasr extensions to get-reg-list test
>
> Documentation/arch/riscv/hwprobe.rst | 5 +-
> .../devicetree/bindings/riscv/extensions.yaml | 5 +
> arch/riscv/include/asm/atomic.h | 70 ++++++++-
> arch/riscv/include/asm/barrier.h | 91 +++++++++--
> arch/riscv/include/asm/cmpxchg.h | 144 +++++++++---------
> arch/riscv/include/asm/fence.h | 4 -
> arch/riscv/include/asm/hwcap.h | 1 +
> arch/riscv/include/asm/insn-def.h | 79 ++++++++++
> arch/riscv/include/uapi/asm/hwprobe.h | 1 +
> arch/riscv/include/uapi/asm/kvm.h | 1 +
> arch/riscv/kernel/cpufeature.c | 1 +
> arch/riscv/kernel/sys_hwprobe.c | 1 +
> arch/riscv/kvm/vcpu_onereg.c | 2 +
> .../selftests/kvm/riscv/get-reg-list.c | 4 +
> 14 files changed, 314 insertions(+), 95 deletions(-)
>
> --
> 2.20.1
>
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^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH v4 00/10] riscv: Add Zalasr ISA extension support
2025-10-20 4:20 [PATCH v4 00/10] riscv: Add Zalasr ISA extension support Xu Lu
` (5 preceding siblings ...)
2025-10-24 21:47 ` Andrea Parri
@ 2025-11-19 12:30 ` patchwork-bot+linux-riscv
2025-11-19 15:42 ` Paul Walmsley
6 siblings, 1 reply; 13+ messages in thread
From: patchwork-bot+linux-riscv @ 2025-11-19 12:30 UTC (permalink / raw)
To: Xu Lu
Cc: linux-riscv, corbet, paul.walmsley, palmer, aou, alex, robh,
krzk+dt, conor+dt, will, peterz, boqun.feng, mark.rutland, anup,
atish.patra, pbonzini, shuah, parri.andrea, ajones, brs, guoren,
linux-doc, linux-kernel, devicetree, kvm, kvm-riscv,
linux-kselftest, apw, joe, lukas.bulwahn
Hello:
This series was applied to riscv/linux.git (for-next)
by Paul Walmsley <pjw@kernel.org>:
On Mon, 20 Oct 2025 12:20:46 +0800 you wrote:
> This patch adds support for the Zalasr ISA extension, which supplies the
> real load acquire/store release instructions.
>
> The specification can be found here:
> https://github.com/riscv/riscv-zalasr/blob/main/chapter2.adoc
>
> This patch seires has been tested with ltp on Qemu with Brensan's zalasr
> support patch[1].
>
> [...]
Here is the summary with links:
- [v4,01/10] riscv: Add ISA extension parsing for Zalasr
https://git.kernel.org/riscv/c/0597b9c8627e
- [v4,02/10] dt-bindings: riscv: Add Zalasr ISA extension description
https://git.kernel.org/riscv/c/6e2a0ff70abe
- [v4,03/10] riscv: hwprobe: Export Zalasr extension
https://git.kernel.org/riscv/c/d5e20628a882
- [v4,04/10] riscv: Introduce Zalasr instructions
https://git.kernel.org/riscv/c/c4139ea6717c
- [v4,05/10] riscv: Apply Zalasr to smp_load_acquire/smp_store_release
(no matching commit)
- [v4,06/10] riscv: Apply acquire/release semantics to arch_xchg/arch_cmpxchg operations
(no matching commit)
- [v4,07/10] riscv: Apply acquire/release semantics to arch_atomic operations
(no matching commit)
- [v4,08/10] riscv: Remove arch specific __atomic_acquire/release_fence
(no matching commit)
- [v4,09/10] RISC-V: KVM: Allow Zalasr extensions for Guest/VM
(no matching commit)
- [v4,10/10] RISC-V: KVM: selftests: Add Zalasr extensions to get-reg-list test
(no matching commit)
You are awesome, thank you!
--
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^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH v4 00/10] riscv: Add Zalasr ISA extension support
2025-11-19 12:30 ` patchwork-bot+linux-riscv
@ 2025-11-19 15:42 ` Paul Walmsley
2025-11-19 15:57 ` 路旭
0 siblings, 1 reply; 13+ messages in thread
From: Paul Walmsley @ 2025-11-19 15:42 UTC (permalink / raw)
To: patchwork-bot+linux-riscv
Cc: Xu Lu, linux-riscv, corbet, paul.walmsley, palmer, aou, alex,
robh, krzk+dt, conor+dt, will, peterz, boqun.feng, mark.rutland,
anup, atish.patra, pbonzini, shuah, parri.andrea, ajones, brs,
guoren, linux-doc, linux-kernel, devicetree, kvm, kvm-riscv,
linux-kselftest, apw, joe, lukas.bulwahn
Folks,
On Wed, 19 Nov 2025, patchwork-bot+linux-riscv@kernel.org wrote:
> This series was applied to riscv/linux.git (for-next)
> by Paul Walmsley <pjw@kernel.org>:
This actually isn't true; I've only applied the first four patches (see
below).
> On Mon, 20 Oct 2025 12:20:46 +0800 you wrote:
> > This patch adds support for the Zalasr ISA extension, which supplies the
> > real load acquire/store release instructions.
> >
> > The specification can be found here:
> > https://github.com/riscv/riscv-zalasr/blob/main/chapter2.adoc
> >
> > This patch seires has been tested with ltp on Qemu with Brensan's zalasr
> > support patch[1].
> >
> > [...]
>
> Here is the summary with links:
> - [v4,01/10] riscv: Add ISA extension parsing for Zalasr
> https://git.kernel.org/riscv/c/0597b9c8627e
> - [v4,02/10] dt-bindings: riscv: Add Zalasr ISA extension description
> https://git.kernel.org/riscv/c/6e2a0ff70abe
> - [v4,03/10] riscv: hwprobe: Export Zalasr extension
> https://git.kernel.org/riscv/c/d5e20628a882
> - [v4,04/10] riscv: Introduce Zalasr instructions
> https://git.kernel.org/riscv/c/c4139ea6717c
> - [v4,05/10] riscv: Apply Zalasr to smp_load_acquire/smp_store_release
> (no matching commit)
> - [v4,06/10] riscv: Apply acquire/release semantics to arch_xchg/arch_cmpxchg operations
> (no matching commit)
> - [v4,07/10] riscv: Apply acquire/release semantics to arch_atomic operations
> (no matching commit)
> - [v4,08/10] riscv: Remove arch specific __atomic_acquire/release_fence
> (no matching commit)
> - [v4,09/10] RISC-V: KVM: Allow Zalasr extensions for Guest/VM
> (no matching commit)
> - [v4,10/10] RISC-V: KVM: selftests: Add Zalasr extensions to get-reg-list test
> (no matching commit)
In terms of patches 5-8, we're still waiting for Xu Lu to update the
patches based on Andrea's feedback. Xu Lu, are you still planning to
update these?
- Paul
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v4 00/10] riscv: Add Zalasr ISA extension support
2025-11-19 15:42 ` Paul Walmsley
@ 2025-11-19 15:57 ` 路旭
0 siblings, 0 replies; 13+ messages in thread
From: 路旭 @ 2025-11-19 15:57 UTC (permalink / raw)
To: Paul Walmsley
Cc: patchwork-bot+linux-riscv, linux-riscv, corbet, paul.walmsley,
palmer, aou, alex, robh, krzk+dt, conor+dt, will, peterz,
boqun.feng, mark.rutland, anup, atish.patra, pbonzini, shuah,
parri.andrea, ajones, brs, guoren, linux-doc, linux-kernel,
devicetree, kvm, kvm-riscv, linux-kselftest, apw, joe,
lukas.bulwahn
Hi Paul,
I will continue with this work. And thanks for Andrea's feedback.
Best Regards,
Xu Lu
> From: "Paul Walmsley"<pjw@kernel.org>
> Date: Wed, Nov 19, 2025, 23:42
> Subject: Re: [PATCH v4 00/10] riscv: Add Zalasr ISA extension support
> To: <patchwork-bot+linux-riscv@kernel.org>
> Cc: "Xu Lu"<luxu.kernel@bytedance.com>, <linux-riscv@lists.infradead.org>, <corbet@lwn.net>, <paul.walmsley@sifive.com>, <palmer@dabbelt.com>, <aou@eecs.berkeley.edu>, <alex@ghiti.fr>, <robh@kernel.org>, <krzk+dt@kernel.org>, <conor+dt@kernel.org>, <will@kernel.org>, <peterz@infradead.org>, <boqun.feng@gmail.com>, <mark.rutland@arm.com>, <anup@brainfault.org>, <atish.patra@linux.dev>, <pbonzini@redhat.com>, <shuah@kernel.org>, <parri.andrea@gmail.com>, <ajones@ventanamicro.com>, <brs@rivosinc.com>, <guoren@kernel.org>, <linux-doc@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>, <kvm@vger.kernel.org>, <kvm-riscv@lists.infradead.org>, <linux-kselftest@vger.kernel.org>, <apw@canonical.com>, <joe@perches.com>, <lukas.bulwahn@gmail.com>
> Folks,
>
> On Wed, 19 Nov 2025, patchwork-bot+linux-riscv@kernel.org wrote:
>
> > This series was applied to riscv/linux.git (for-next)
> > by Paul Walmsley <pjw@kernel.org>:
>
> This actually isn't true; I've only applied the first four patches (see
> below).
>
> > On Mon, 20 Oct 2025 12:20:46 +0800 you wrote:
> > > This patch adds support for the Zalasr ISA extension, which supplies the
> > > real load acquire/store release instructions.
> > >
> > > The specification can be found here:
> > > https://github.com/riscv/riscv-zalasr/blob/main/chapter2.adoc
> > >
> > > This patch seires has been tested with ltp on Qemu with Brensan's zalasr
> > > support patch[1].
> > >
> > > [...]
> >
> > Here is the summary with links:
> > - [v4,01/10] riscv: Add ISA extension parsing for Zalasr
> > https://git.kernel.org/riscv/c/0597b9c8627e
> > - [v4,02/10] dt-bindings: riscv: Add Zalasr ISA extension description
> > https://git.kernel.org/riscv/c/6e2a0ff70abe
> > - [v4,03/10] riscv: hwprobe: Export Zalasr extension
> > https://git.kernel.org/riscv/c/d5e20628a882
> > - [v4,04/10] riscv: Introduce Zalasr instructions
> > https://git.kernel.org/riscv/c/c4139ea6717c
> > - [v4,05/10] riscv: Apply Zalasr to smp_load_acquire/smp_store_release
> > (no matching commit)
> > - [v4,06/10] riscv: Apply acquire/release semantics to arch_xchg/arch_cmpxchg operations
> > (no matching commit)
> > - [v4,07/10] riscv: Apply acquire/release semantics to arch_atomic operations
> > (no matching commit)
> > - [v4,08/10] riscv: Remove arch specific __atomic_acquire/release_fence
> > (no matching commit)
> > - [v4,09/10] RISC-V: KVM: Allow Zalasr extensions for Guest/VM
> > (no matching commit)
> > - [v4,10/10] RISC-V: KVM: selftests: Add Zalasr extensions to get-reg-list test
> > (no matching commit)
>
> In terms of patches 5-8, we're still waiting for Xu Lu to update the
> patches based on Andrea's feedback. Xu Lu, are you still planning to
> update these?
>
>
> - Paul
>
--
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^ permalink raw reply [flat|nested] 13+ messages in thread