From: Charlie Jenkins <charlie@rivosinc.com>
To: "Clément Léger" <cleger@rivosinc.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@atishpatra.org>,
Shuah Khan <shuah@kernel.org>, Jonathan Corbet <corbet@lwn.net>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-doc@vger.kernel.org, kvm@vger.kernel.org,
kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org,
Samuel Holland <samuel.holland@sifive.com>,
Andrew Jones <ajones@ventanamicro.com>,
Deepak Gupta <debug@rivosinc.com>
Subject: Re: [PATCH v8 09/14] riscv: misaligned: move emulated access uniformity check in a function
Date: Fri, 23 May 2025 11:30:42 -0700 [thread overview]
Message-ID: <aDC-0qe5STR7ow4m@ghost> (raw)
In-Reply-To: <20250523101932.1594077-10-cleger@rivosinc.com>
On Fri, May 23, 2025 at 12:19:26PM +0200, Clément Léger wrote:
> Split the code that check for the uniformity of misaligned accesses
> performance on all cpus from check_unaligned_access_emulated_all_cpus()
> to its own function which will be used for delegation check. No
> functional changes intended.
>
> Signed-off-by: Clément Léger <cleger@rivosinc.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> ---
> arch/riscv/kernel/traps_misaligned.c | 20 ++++++++++++++------
> 1 file changed, 14 insertions(+), 6 deletions(-)
>
> diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c
> index f1b2af515592..7ecaa8103fe7 100644
> --- a/arch/riscv/kernel/traps_misaligned.c
> +++ b/arch/riscv/kernel/traps_misaligned.c
> @@ -645,6 +645,18 @@ bool __init check_vector_unaligned_access_emulated_all_cpus(void)
> }
> #endif
>
> +static bool all_cpus_unaligned_scalar_access_emulated(void)
> +{
> + int cpu;
> +
> + for_each_online_cpu(cpu)
> + if (per_cpu(misaligned_access_speed, cpu) !=
> + RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED)
> + return false;
> +
> + return true;
> +}
This ends up wasting time when !CONFIG_RISCV_SCALAR_MISALIGNED since it
will always return false in that case. Maybe there is a way to simplify
the ifdefs and still have performant code, but I don't think this is a
big enough problem to prevent this patch from merging.
Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>
Tested-by: Charlie Jenkins <charlie@rivosinc.com>
> +
> #ifdef CONFIG_RISCV_SCALAR_MISALIGNED
>
> static bool unaligned_ctl __read_mostly;
> @@ -683,8 +695,6 @@ static int cpu_online_check_unaligned_access_emulated(unsigned int cpu)
>
> bool __init check_unaligned_access_emulated_all_cpus(void)
> {
> - int cpu;
> -
> /*
> * We can only support PR_UNALIGN controls if all CPUs have misaligned
> * accesses emulated since tasks requesting such control can run on any
> @@ -692,10 +702,8 @@ bool __init check_unaligned_access_emulated_all_cpus(void)
> */
> on_each_cpu(check_unaligned_access_emulated, NULL, 1);
>
> - for_each_online_cpu(cpu)
> - if (per_cpu(misaligned_access_speed, cpu)
> - != RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED)
> - return false;
> + if (!all_cpus_unaligned_scalar_access_emulated())
> + return false;
>
> unaligned_ctl = true;
> return true;
> --
> 2.49.0
>
--
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next prev parent reply other threads:[~2025-05-23 18:30 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-23 10:19 [PATCH v8 00/14] riscv: add SBI FWFT misaligned exception delegation support Clément Léger
2025-05-23 10:19 ` [PATCH v8 01/14] riscv: sbi: add Firmware Feature (FWFT) SBI extensions definitions Clément Léger
2025-05-23 10:19 ` [PATCH v8 02/14] riscv: sbi: remove useless parenthesis Clément Léger
2025-05-23 10:19 ` [PATCH v8 03/14] riscv: sbi: add new SBI error mappings Clément Léger
2025-05-23 10:19 ` [PATCH v8 04/14] riscv: sbi: add FWFT extension interface Clément Léger
2025-05-23 10:19 ` [PATCH v8 05/14] riscv: sbi: add SBI FWFT extension calls Clément Léger
2025-05-23 10:19 ` [PATCH v8 06/14] riscv: misaligned: request misaligned exception from SBI Clément Léger
2025-05-23 10:19 ` [PATCH v8 07/14] riscv: misaligned: use on_each_cpu() for scalar misaligned access probing Clément Léger
2025-05-23 18:37 ` Charlie Jenkins
2025-05-23 10:19 ` [PATCH v8 08/14] riscv: misaligned: declare misaligned_access_speed under CONFIG_RISCV_MISALIGNED Clément Léger
2025-05-23 18:36 ` Charlie Jenkins
2025-05-29 12:43 ` Andrew Jones
2025-05-23 10:19 ` [PATCH v8 09/14] riscv: misaligned: move emulated access uniformity check in a function Clément Léger
2025-05-23 18:30 ` Charlie Jenkins [this message]
2025-05-23 19:21 ` Clément Léger
2025-05-26 8:41 ` Andrew Jones
2025-05-26 9:38 ` Clément Léger
2025-05-23 10:19 ` [PATCH v8 10/14] riscv: misaligned: add a function to check misalign trap delegability Clément Léger
2025-05-23 18:39 ` Charlie Jenkins
2025-05-23 10:19 ` [PATCH v8 11/14] RISC-V: KVM: add SBI extension init()/deinit() functions Clément Léger
2025-06-12 13:24 ` Anup Patel
2025-05-23 10:19 ` [PATCH v8 12/14] RISC-V: KVM: add SBI extension reset callback Clément Léger
2025-06-12 13:24 ` Anup Patel
2025-05-23 10:19 ` [PATCH v8 13/14] RISC-V: KVM: add support for FWFT SBI extension Clément Léger
2025-05-23 13:05 ` Radim Krčmář
2025-05-23 15:29 ` Clément Léger
2025-05-23 16:27 ` Radim Krčmář
2025-05-23 18:02 ` Atish Patra
2025-05-23 19:23 ` Clément Léger
2025-05-26 8:58 ` Radim Krčmář
2025-06-12 13:25 ` Anup Patel
2025-05-23 10:19 ` [PATCH v8 14/14] RISC-V: KVM: add support for SBI_FWFT_MISALIGNED_DELEG Clément Léger
2025-05-23 13:08 ` Radim Krčmář
2025-06-12 13:26 ` Anup Patel
2025-06-04 18:02 ` [PATCH v8 00/14] riscv: add SBI FWFT misaligned exception delegation support Palmer Dabbelt
2025-06-04 19:32 ` Charlie Jenkins
2025-06-05 7:12 ` Alexandre Ghiti
2025-06-05 1:30 ` patchwork-bot+linux-riscv
2025-08-10 21:12 ` patchwork-bot+linux-riscv
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