* [PATCH 0/4] RISC-V: KVM: Add Zicfiss/Zicfilp support
@ 2025-12-01 1:28 zhouquan
2025-12-01 1:28 ` [PATCH 1/4] RISC-V: KVM: Allow zicfiss/zicfilp exts for Guest/VM zhouquan
` (3 more replies)
0 siblings, 4 replies; 9+ messages in thread
From: zhouquan @ 2025-12-01 1:28 UTC (permalink / raw)
To: anup, ajones, atishp, paul.walmsley, palmer
Cc: linux-kernel, linux-riscv, kvm, kvm-riscv, Quan Zhou
From: Quan Zhou <zhouquan@iscas.ac.cn>
This patchset is based on `riscv control-flow integrity for usermode` [1].
Add Zicfiss/Zicfilp [2] and sbi fwft [3] support for riscv kvm.
[1] - https://lore.kernel.org/all/20251112-v5_user_cfi_series-v23-0-b55691eacf4f@rivosinc.com/
[2] - https://github.com/riscv/riscv-cfi
[3] - https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/src/ext-firmware-features.adoc
Quan Zhou (4):
RISC-V: KVM: Allow zicfiss/zicfilp exts for Guest/VM
RISC-V: KVM: Add support for software check exception
RISC-V: KVM: Add suuport for zicfiss/zicfilp/svadu FWFT features
KVM: riscv: selftests: Add zicfiss/zicfilp/svadu and SBI FWFT to
get-reg-list test
arch/riscv/include/asm/csr.h | 1 +
arch/riscv/include/asm/kvm_host.h | 3 +-
arch/riscv/include/uapi/asm/kvm.h | 5 +
arch/riscv/kvm/vcpu.c | 6 +
arch/riscv/kvm/vcpu_exit.c | 3 +
arch/riscv/kvm/vcpu_onereg.c | 2 +
arch/riscv/kvm/vcpu_sbi_fwft.c | 129 ++++++++++++++++++
.../selftests/kvm/riscv/get-reg-list.c | 26 ++++
8 files changed, 174 insertions(+), 1 deletion(-)
--
2.34.1
--
kvm-riscv mailing list
kvm-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/kvm-riscv
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 1/4] RISC-V: KVM: Allow zicfiss/zicfilp exts for Guest/VM
2025-12-01 1:28 [PATCH 0/4] RISC-V: KVM: Add Zicfiss/Zicfilp support zhouquan
@ 2025-12-01 1:28 ` zhouquan
2025-12-03 17:19 ` Deepak Gupta
2025-12-01 1:28 ` [PATCH 2/4] RISC-V: KVM: Add support for software check exception zhouquan
` (2 subsequent siblings)
3 siblings, 1 reply; 9+ messages in thread
From: zhouquan @ 2025-12-01 1:28 UTC (permalink / raw)
To: anup, ajones, atishp, paul.walmsley, palmer
Cc: linux-kernel, linux-riscv, kvm, kvm-riscv, Quan Zhou
From: Quan Zhou <zhouquan@iscas.ac.cn>
Extend the KVM ISA extension ONE_REG interface to allow KVM user
space to detect and enable zicfiss/zicfilp exts for Guest/VM,
the rules defined in the spec [1] are as follows:
---
1) Zicfiss extension introduces the SSE field (bit 3) in henvcfg.
If the SSE field is set to 1, the Zicfiss extension is activated
in VS-mode. When the SSE field is 0, the Zicfiss extension remains
inactive in VS-mode.
2) Zicfilp extension introduces the LPE field (bit 2) in henvcfg.
When the LPE field is set to 1, the Zicfilp extension is enabled
in VS-mode. When the LPE field is 0, the Zicfilp extension is not
enabled in VS-mode.
[1] - https://github.com/riscv/riscv-cfi
Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn>
---
arch/riscv/include/uapi/asm/kvm.h | 2 ++
arch/riscv/kvm/vcpu.c | 6 ++++++
arch/riscv/kvm/vcpu_onereg.c | 2 ++
3 files changed, 10 insertions(+)
diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
index 759a4852c09a..7ca087848a43 100644
--- a/arch/riscv/include/uapi/asm/kvm.h
+++ b/arch/riscv/include/uapi/asm/kvm.h
@@ -190,6 +190,8 @@ enum KVM_RISCV_ISA_EXT_ID {
KVM_RISCV_ISA_EXT_ZFBFMIN,
KVM_RISCV_ISA_EXT_ZVFBFMIN,
KVM_RISCV_ISA_EXT_ZVFBFWMA,
+ KVM_RISCV_ISA_EXT_ZICFILP,
+ KVM_RISCV_ISA_EXT_ZICFISS,
KVM_RISCV_ISA_EXT_MAX,
};
diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
index 5ce35aba6069..098d77f9a886 100644
--- a/arch/riscv/kvm/vcpu.c
+++ b/arch/riscv/kvm/vcpu.c
@@ -557,6 +557,12 @@ static void kvm_riscv_vcpu_setup_config(struct kvm_vcpu *vcpu)
if (riscv_isa_extension_available(isa, ZICBOZ))
cfg->henvcfg |= ENVCFG_CBZE;
+ if (riscv_isa_extension_available(isa, ZICFILP))
+ cfg->henvcfg |= ENVCFG_LPE;
+
+ if (riscv_isa_extension_available(isa, ZICFISS))
+ cfg->henvcfg |= ENVCFG_SSE;
+
if (riscv_isa_extension_available(isa, SVADU) &&
!riscv_isa_extension_available(isa, SVADE))
cfg->henvcfg |= ENVCFG_ADUE;
diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c
index 865dae903aa0..3d05a4bafd9b 100644
--- a/arch/riscv/kvm/vcpu_onereg.c
+++ b/arch/riscv/kvm/vcpu_onereg.c
@@ -72,6 +72,8 @@ static const unsigned long kvm_isa_ext_arr[] = {
KVM_ISA_EXT_ARR(ZICBOP),
KVM_ISA_EXT_ARR(ZICBOZ),
KVM_ISA_EXT_ARR(ZICCRSE),
+ KVM_ISA_EXT_ARR(ZICFILP),
+ KVM_ISA_EXT_ARR(ZICFISS),
KVM_ISA_EXT_ARR(ZICNTR),
KVM_ISA_EXT_ARR(ZICOND),
KVM_ISA_EXT_ARR(ZICSR),
--
2.34.1
--
kvm-riscv mailing list
kvm-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/kvm-riscv
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 2/4] RISC-V: KVM: Add support for software check exception
2025-12-01 1:28 [PATCH 0/4] RISC-V: KVM: Add Zicfiss/Zicfilp support zhouquan
2025-12-01 1:28 ` [PATCH 1/4] RISC-V: KVM: Allow zicfiss/zicfilp exts for Guest/VM zhouquan
@ 2025-12-01 1:28 ` zhouquan
2025-12-01 1:28 ` [PATCH 3/4] RISC-V: KVM: Add suuport for zicfiss/zicfilp/svadu FWFT features zhouquan
2025-12-01 1:29 ` [PATCH 4/4] KVM: riscv: selftests: Add zicfiss/zicfilp/svadu and SBI FWFT to get-reg-list test zhouquan
3 siblings, 0 replies; 9+ messages in thread
From: zhouquan @ 2025-12-01 1:28 UTC (permalink / raw)
To: anup, ajones, atishp, paul.walmsley, palmer
Cc: linux-kernel, linux-riscv, kvm, kvm-riscv, Quan Zhou
From: Quan Zhou <zhouquan@iscas.ac.cn>
zicfiss / zicfilp introduces a new exception to priv isa `software check
exception` with cause code = 18. Delegate this exception to VS mode because
cfi violations in VU/VS will be reported via this exception.
RISC-V KVM should ensure that even if the SBI implementation ignores
hedeleg settings and routes VS-mode software check exceptions to HS mode,
KVM still correctly forwards them to the guest. Otherwise, these exceptions
would exit to userspace and terminate the guest.
Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn>
---
arch/riscv/include/asm/csr.h | 1 +
arch/riscv/include/asm/kvm_host.h | 3 ++-
arch/riscv/kvm/vcpu_exit.c | 3 +++
3 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 4a37a98398ad..9f10ef69de30 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -108,6 +108,7 @@
#define EXC_INST_PAGE_FAULT 12
#define EXC_LOAD_PAGE_FAULT 13
#define EXC_STORE_PAGE_FAULT 15
+#define EXC_SOFTWARE_CHECK 18
#define EXC_INST_GUEST_PAGE_FAULT 20
#define EXC_LOAD_GUEST_PAGE_FAULT 21
#define EXC_VIRTUAL_INST_FAULT 22
diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h
index 4d794573e3db..0bb4da1c73df 100644
--- a/arch/riscv/include/asm/kvm_host.h
+++ b/arch/riscv/include/asm/kvm_host.h
@@ -53,7 +53,8 @@
BIT(EXC_SYSCALL) | \
BIT(EXC_INST_PAGE_FAULT) | \
BIT(EXC_LOAD_PAGE_FAULT) | \
- BIT(EXC_STORE_PAGE_FAULT))
+ BIT(EXC_STORE_PAGE_FAULT)) | \
+ BIT(EXC_SOFTWARE_CHECK)
#define KVM_HIDELEG_DEFAULT (BIT(IRQ_VS_SOFT) | \
BIT(IRQ_VS_TIMER) | \
diff --git a/arch/riscv/kvm/vcpu_exit.c b/arch/riscv/kvm/vcpu_exit.c
index 0bb0c51e3c89..5ab8e87ed248 100644
--- a/arch/riscv/kvm/vcpu_exit.c
+++ b/arch/riscv/kvm/vcpu_exit.c
@@ -243,6 +243,9 @@ int kvm_riscv_vcpu_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
run->exit_reason = KVM_EXIT_DEBUG;
ret = 0;
break;
+ case EXC_SOFTWARE_CHECK:
+ ret = vcpu_redirect(vcpu, trap);
+ break;
default:
break;
}
--
2.34.1
--
kvm-riscv mailing list
kvm-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/kvm-riscv
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 3/4] RISC-V: KVM: Add suuport for zicfiss/zicfilp/svadu FWFT features
2025-12-01 1:28 [PATCH 0/4] RISC-V: KVM: Add Zicfiss/Zicfilp support zhouquan
2025-12-01 1:28 ` [PATCH 1/4] RISC-V: KVM: Allow zicfiss/zicfilp exts for Guest/VM zhouquan
2025-12-01 1:28 ` [PATCH 2/4] RISC-V: KVM: Add support for software check exception zhouquan
@ 2025-12-01 1:28 ` zhouquan
2025-12-03 10:52 ` kernel test robot
2025-12-01 1:29 ` [PATCH 4/4] KVM: riscv: selftests: Add zicfiss/zicfilp/svadu and SBI FWFT to get-reg-list test zhouquan
3 siblings, 1 reply; 9+ messages in thread
From: zhouquan @ 2025-12-01 1:28 UTC (permalink / raw)
To: anup, ajones, atishp, paul.walmsley, palmer
Cc: linux-kernel, linux-riscv, kvm, kvm-riscv, Quan Zhou
From: Quan Zhou <zhouquan@iscas.ac.cn>
Add support in KVM SBI FWFT extension to allow VS-mode to request
SBI_FWFT_{LANDING_PAD/SHADOW_STACK/PTE_AD_HW_UPDATING}.
Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn>
---
arch/riscv/include/uapi/asm/kvm.h | 3 +
arch/riscv/kvm/vcpu_sbi_fwft.c | 129 ++++++++++++++++++++++++++++++
2 files changed, 132 insertions(+)
diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
index 7ca087848a43..d93b70d89010 100644
--- a/arch/riscv/include/uapi/asm/kvm.h
+++ b/arch/riscv/include/uapi/asm/kvm.h
@@ -232,6 +232,9 @@ struct kvm_riscv_sbi_fwft_feature {
struct kvm_riscv_sbi_fwft {
struct kvm_riscv_sbi_fwft_feature misaligned_deleg;
struct kvm_riscv_sbi_fwft_feature pointer_masking;
+ struct kvm_riscv_sbi_fwft_feature landing_pad;
+ struct kvm_riscv_sbi_fwft_feature shadow_stack;
+ struct kvm_riscv_sbi_fwft_feature pte_ad_hw_updating;
};
/* Possible states for kvm_riscv_timer */
diff --git a/arch/riscv/kvm/vcpu_sbi_fwft.c b/arch/riscv/kvm/vcpu_sbi_fwft.c
index 62cc9c3d5759..0dc0e70fc83b 100644
--- a/arch/riscv/kvm/vcpu_sbi_fwft.c
+++ b/arch/riscv/kvm/vcpu_sbi_fwft.c
@@ -213,6 +213,108 @@ static long kvm_sbi_fwft_get_pointer_masking_pmlen(struct kvm_vcpu *vcpu,
return SBI_SUCCESS;
}
+static long kvm_sbi_fwft_set_henvcfg_flag(struct kvm_vcpu *vcpu,
+ struct kvm_sbi_fwft_config *conf,
+ bool one_reg_access, unsigned long value,
+ unsigned long flag)
+{
+ struct kvm_vcpu_config *cfg = &vcpu->arch.cfg;
+
+ if (value == 1)
+ cfg->henvcfg |= flag;
+ else if (value == 0)
+ cfg->henvcfg &= ~flag;
+ else
+ return SBI_ERR_INVALID_PARAM;
+
+ if (!one_reg_access)
+ csr_write(CSR_HENVCFG, cfg->henvcfg);
+
+ return SBI_SUCCESS;
+}
+
+static bool kvm_sbi_fwft_pointer_landing_pad_supported(struct kvm_vcpu *vcpu)
+{
+ return riscv_isa_extension_available(vcpu->arch.isa, ZICFILP);
+}
+
+static void kvm_sbi_fwft_reset_landing_pad(struct kvm_vcpu *vcpu)
+{
+ vcpu->arch.cfg.henvcfg &= ~ENVCFG_LPE;
+}
+
+static long kvm_sbi_fwft_set_landing_pad(struct kvm_vcpu *vcpu,
+ struct kvm_sbi_fwft_config *conf,
+ bool one_reg_access, unsigned long value)
+{
+ return kvm_sbi_fwft_set_henvcfg_flag(vcpu, conf, one_reg_access, value, ENVCFG_LPE);
+}
+
+static long kvm_sbi_fwft_get_landing_pad(struct kvm_vcpu *vcpu,
+ struct kvm_sbi_fwft_config *conf,
+ bool one_reg_access, unsigned long *value)
+{
+ struct kvm_vcpu_config *cfg = &vcpu->arch.cfg;
+
+ *value = (cfg->henvcfg & ENVCFG_LPE) == ENVCFG_LPE;
+ return SBI_SUCCESS;
+}
+
+static bool kvm_sbi_fwft_pointer_shadow_stack_supported(struct kvm_vcpu *vcpu)
+{
+ return riscv_isa_extension_available(vcpu->arch.isa, ZICFISS);
+}
+
+static void kvm_sbi_fwft_reset_shadow_stack(struct kvm_vcpu *vcpu)
+{
+ vcpu->arch.cfg.henvcfg &= ~ENVCFG_SSE;
+}
+
+static long kvm_sbi_fwft_set_shadow_stack(struct kvm_vcpu *vcpu,
+ struct kvm_sbi_fwft_config *conf,
+ bool one_reg_access, unsigned long value)
+{
+ return kvm_sbi_fwft_set_henvcfg_flag(vcpu, conf, one_reg_access, value, ENVCFG_SSE);
+}
+
+static long kvm_sbi_fwft_get_shadow_stack(struct kvm_vcpu *vcpu,
+ struct kvm_sbi_fwft_config *conf,
+ bool one_reg_access, unsigned long *value)
+{
+ struct kvm_vcpu_config *cfg = &vcpu->arch.cfg;
+
+ *value = (cfg->henvcfg & ENVCFG_SSE) == ENVCFG_SSE;
+ return SBI_SUCCESS;
+}
+
+static bool kvm_sbi_fwft_pointer_pte_ad_hw_updating_supported(struct kvm_vcpu *vcpu)
+{
+ return riscv_isa_extension_available(vcpu->arch.isa, SVADU) &&
+ !riscv_isa_extension_available(vcpu->arch.isa, SVADE);
+}
+
+static void kvm_sbi_fwft_reset_pte_ad_hw_updating(struct kvm_vcpu *vcpu)
+{
+ vcpu->arch.cfg.henvcfg &= ~ENVCFG_ADUE;
+}
+
+static long kvm_sbi_fwft_set_pte_ad_hw_updating(struct kvm_vcpu *vcpu,
+ struct kvm_sbi_fwft_config *conf,
+ bool one_reg_access, unsigned long value)
+{
+ return kvm_sbi_fwft_set_henvcfg_flag(vcpu, conf, one_reg_access, value, ENVCFG_ADUE);
+}
+
+static long kvm_sbi_fwft_get_pte_ad_hw_updating(struct kvm_vcpu *vcpu,
+ struct kvm_sbi_fwft_config *conf,
+ bool one_reg_access, unsigned long *value)
+{
+ struct kvm_vcpu_config *cfg = &vcpu->arch.cfg;
+
+ *value = (cfg->henvcfg & ENVCFG_ADUE) == ENVCFG_ADUE;
+ return SBI_SUCCESS;
+}
+
#endif
static const struct kvm_sbi_fwft_feature features[] = {
@@ -236,6 +338,33 @@ static const struct kvm_sbi_fwft_feature features[] = {
.get = kvm_sbi_fwft_get_pointer_masking_pmlen,
},
#endif
+ {
+ .id = SBI_FWFT_LANDING_PAD,
+ .first_reg_num = offsetof(struct kvm_riscv_sbi_fwft, landing_pad.enable) /
+ sizeof(unsigned long),
+ .supported = kvm_sbi_fwft_landing_pad_supported,
+ .reset = kvm_sbi_fwft_reset_landing_pad,
+ .set = kvm_sbi_fwft_set_landing_pad,
+ .get = kvm_sbi_fwft_get_landing_pad,
+ },
+ {
+ .id = SBI_FWFT_SHADOW_STACK,
+ .first_reg_num = offsetof(struct kvm_riscv_sbi_fwft, shadow_stack.enable) /
+ sizeof(unsigned long),
+ .supported = kvm_sbi_fwft_shadow_stack_supported,
+ .reset = kvm_sbi_fwft_reset_shadow_stack,
+ .set = kvm_sbi_fwft_set_shadow_stack,
+ .get = kvm_sbi_fwft_get_shadow_stack,
+ },
+ {
+ .id = SBI_FWFT_PTE_AD_HW_UPDATING,
+ .first_reg_num = offsetof(struct kvm_riscv_sbi_fwft, pte_ad_hw_updating.enable) /
+ sizeof(unsigned long),
+ .supported = kvm_sbi_fwft_pte_ad_hw_updating_supported,
+ .reset = kvm_sbi_fwft_reset_pte_ad_hw_updating,
+ .set = kvm_sbi_fwft_set_pte_ad_hw_updating,
+ .get = kvm_sbi_fwft_get_pte_ad_hw_updating,
+ },
};
static const struct kvm_sbi_fwft_feature *kvm_sbi_fwft_regnum_to_feature(unsigned long reg_num)
--
2.34.1
--
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http://lists.infradead.org/mailman/listinfo/kvm-riscv
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 4/4] KVM: riscv: selftests: Add zicfiss/zicfilp/svadu and SBI FWFT to get-reg-list test
2025-12-01 1:28 [PATCH 0/4] RISC-V: KVM: Add Zicfiss/Zicfilp support zhouquan
` (2 preceding siblings ...)
2025-12-01 1:28 ` [PATCH 3/4] RISC-V: KVM: Add suuport for zicfiss/zicfilp/svadu FWFT features zhouquan
@ 2025-12-01 1:29 ` zhouquan
3 siblings, 0 replies; 9+ messages in thread
From: zhouquan @ 2025-12-01 1:29 UTC (permalink / raw)
To: anup, ajones, atishp, paul.walmsley, palmer
Cc: linux-kernel, linux-riscv, kvm, kvm-riscv, Quan Zhou
From: Quan Zhou <zhouquan@iscas.ac.cn>
The KVM RISC-V allows zicfiss/zicfilp/svadu and SBI FWFT for Guest/VM,
so add them to get-reg-list test.
Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn>
---
.../selftests/kvm/riscv/get-reg-list.c | 26 +++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c
index 705ab3d7778b..cd9304943c9c 100644
--- a/tools/testing/selftests/kvm/riscv/get-reg-list.c
+++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c
@@ -87,6 +87,8 @@ bool filter_reg(__u64 reg)
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOP:
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOZ:
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICCRSE:
+ case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICFILP:
+ case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICFISS:
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICNTR:
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICOND:
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICSR:
@@ -546,6 +548,8 @@ static const char *isa_ext_single_id_to_str(__u64 reg_off)
KVM_ISA_EXT_ARR(ZICBOP),
KVM_ISA_EXT_ARR(ZICBOZ),
KVM_ISA_EXT_ARR(ZICCRSE),
+ KVM_ISA_EXT_ARR(ZICFILP),
+ KVM_ISA_EXT_ARR(ZICFISS),
KVM_ISA_EXT_ARR(ZICNTR),
KVM_ISA_EXT_ARR(ZICOND),
KVM_ISA_EXT_ARR(ZICSR),
@@ -704,6 +708,15 @@ static const char *sbi_fwft_id_to_str(__u64 reg_off)
case 3: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.enable)";
case 4: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.flags)";
case 5: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.value)";
+ case 6: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(landing_pad.enable)";
+ case 7: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(landing_pad.flags)";
+ case 8: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(landing_pad.value)";
+ case 9: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(shadow_stack.enable)";
+ case 10: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(shadow_stack.flags)";
+ case 11: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(shadow_stack.value)";
+ case 12: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pte_ad_hw_updating.enable)";
+ case 13: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pte_ad_hw_updating.flags)";
+ case 14: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pte_ad_hw_updating.value)";
}
return strdup_printf("KVM_REG_RISCV_SBI_FWFT | %lld /* UNKNOWN */", reg_off);
}
@@ -897,6 +910,15 @@ static __u64 sbi_fwft_regs[] = {
KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.enable),
KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.flags),
KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.value),
+ KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(landing_pad.enable),
+ KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(landing_pad.flags),
+ KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(landing_pad.value),
+ KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(shadow_stack.enable),
+ KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(shadow_stack.flags),
+ KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(shadow_stack.value),
+ KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pte_ad_hw_updating.enable),
+ KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pte_ad_hw_updating.flags),
+ KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pte_ad_hw_updating.value),
};
static __u64 zicbom_regs[] = {
@@ -1185,6 +1207,8 @@ KVM_ISA_EXT_SUBLIST_CONFIG(zicbom, ZICBOM);
KVM_ISA_EXT_SUBLIST_CONFIG(zicbop, ZICBOP);
KVM_ISA_EXT_SUBLIST_CONFIG(zicboz, ZICBOZ);
KVM_ISA_EXT_SIMPLE_CONFIG(ziccrse, ZICCRSE);
+KVM_ISA_EXT_SIMPLE_CONFIG(zicfilp, ZICFILP);
+KVM_ISA_EXT_SIMPLE_CONFIG(zicfiss, ZICFISS);
KVM_ISA_EXT_SIMPLE_CONFIG(zicntr, ZICNTR);
KVM_ISA_EXT_SIMPLE_CONFIG(zicond, ZICOND);
KVM_ISA_EXT_SIMPLE_CONFIG(zicsr, ZICSR);
@@ -1264,6 +1288,8 @@ struct vcpu_reg_list *vcpu_configs[] = {
&config_zicbop,
&config_zicboz,
&config_ziccrse,
+ &config_zicfilp,
+ &config_zicfiss,
&config_zicntr,
&config_zicond,
&config_zicsr,
--
2.34.1
--
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^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 3/4] RISC-V: KVM: Add suuport for zicfiss/zicfilp/svadu FWFT features
2025-12-01 1:28 ` [PATCH 3/4] RISC-V: KVM: Add suuport for zicfiss/zicfilp/svadu FWFT features zhouquan
@ 2025-12-03 10:52 ` kernel test robot
0 siblings, 0 replies; 9+ messages in thread
From: kernel test robot @ 2025-12-03 10:52 UTC (permalink / raw)
To: zhouquan, anup, ajones, atishp, paul.walmsley, palmer
Cc: oe-kbuild-all, linux-kernel, linux-riscv, kvm, kvm-riscv,
Quan Zhou
Hi,
kernel test robot noticed the following build errors:
[auto build test ERROR on kvm/queue]
[also build test ERROR on kvm/next linus/master v6.18 next-20251203]
[cannot apply to kvm/linux-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/zhouquan-iscas-ac-cn/RISC-V-KVM-Allow-zicfiss-zicfilp-exts-for-Guest-VM/20251201-094857
base: https://git.kernel.org/pub/scm/virt/kvm/kvm.git queue
patch link: https://lore.kernel.org/r/1793aa636969da0a09d27c9c12f6d5f8f0d1cd21.1764509485.git.zhouquan%40iscas.ac.cn
patch subject: [PATCH 3/4] RISC-V: KVM: Add suuport for zicfiss/zicfilp/svadu FWFT features
config: riscv-randconfig-001-20251203 (https://download.01.org/0day-ci/archive/20251203/202512031835.rfeAWiCJ-lkp@intel.com/config)
compiler: riscv32-linux-gcc (GCC) 14.3.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251203/202512031835.rfeAWiCJ-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202512031835.rfeAWiCJ-lkp@intel.com/
All errors (new ones prefixed by >>):
>> arch/riscv/kvm/vcpu_sbi_fwft.c:345:30: error: 'kvm_sbi_fwft_landing_pad_supported' undeclared here (not in a function)
345 | .supported = kvm_sbi_fwft_landing_pad_supported,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> arch/riscv/kvm/vcpu_sbi_fwft.c:346:26: error: 'kvm_sbi_fwft_reset_landing_pad' undeclared here (not in a function)
346 | .reset = kvm_sbi_fwft_reset_landing_pad,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> arch/riscv/kvm/vcpu_sbi_fwft.c:347:24: error: 'kvm_sbi_fwft_set_landing_pad' undeclared here (not in a function)
347 | .set = kvm_sbi_fwft_set_landing_pad,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> arch/riscv/kvm/vcpu_sbi_fwft.c:348:24: error: 'kvm_sbi_fwft_get_landing_pad' undeclared here (not in a function)
348 | .get = kvm_sbi_fwft_get_landing_pad,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> arch/riscv/kvm/vcpu_sbi_fwft.c:354:30: error: 'kvm_sbi_fwft_shadow_stack_supported' undeclared here (not in a function)
354 | .supported = kvm_sbi_fwft_shadow_stack_supported,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> arch/riscv/kvm/vcpu_sbi_fwft.c:355:26: error: 'kvm_sbi_fwft_reset_shadow_stack' undeclared here (not in a function)
355 | .reset = kvm_sbi_fwft_reset_shadow_stack,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> arch/riscv/kvm/vcpu_sbi_fwft.c:356:24: error: 'kvm_sbi_fwft_set_shadow_stack' undeclared here (not in a function)
356 | .set = kvm_sbi_fwft_set_shadow_stack,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> arch/riscv/kvm/vcpu_sbi_fwft.c:357:24: error: 'kvm_sbi_fwft_get_shadow_stack' undeclared here (not in a function)
357 | .get = kvm_sbi_fwft_get_shadow_stack,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> arch/riscv/kvm/vcpu_sbi_fwft.c:363:30: error: 'kvm_sbi_fwft_pte_ad_hw_updating_supported' undeclared here (not in a function)
363 | .supported = kvm_sbi_fwft_pte_ad_hw_updating_supported,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> arch/riscv/kvm/vcpu_sbi_fwft.c:364:26: error: 'kvm_sbi_fwft_reset_pte_ad_hw_updating' undeclared here (not in a function)
364 | .reset = kvm_sbi_fwft_reset_pte_ad_hw_updating,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> arch/riscv/kvm/vcpu_sbi_fwft.c:365:24: error: 'kvm_sbi_fwft_set_pte_ad_hw_updating' undeclared here (not in a function)
365 | .set = kvm_sbi_fwft_set_pte_ad_hw_updating,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> arch/riscv/kvm/vcpu_sbi_fwft.c:366:24: error: 'kvm_sbi_fwft_get_pte_ad_hw_updating' undeclared here (not in a function)
366 | .get = kvm_sbi_fwft_get_pte_ad_hw_updating,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
vim +/kvm_sbi_fwft_landing_pad_supported +345 arch/riscv/kvm/vcpu_sbi_fwft.c
319
320 static const struct kvm_sbi_fwft_feature features[] = {
321 {
322 .id = SBI_FWFT_MISALIGNED_EXC_DELEG,
323 .first_reg_num = offsetof(struct kvm_riscv_sbi_fwft, misaligned_deleg.enable) /
324 sizeof(unsigned long),
325 .supported = kvm_sbi_fwft_misaligned_delegation_supported,
326 .reset = kvm_sbi_fwft_reset_misaligned_delegation,
327 .set = kvm_sbi_fwft_set_misaligned_delegation,
328 .get = kvm_sbi_fwft_get_misaligned_delegation,
329 },
330 #ifndef CONFIG_32BIT
331 {
332 .id = SBI_FWFT_POINTER_MASKING_PMLEN,
333 .first_reg_num = offsetof(struct kvm_riscv_sbi_fwft, pointer_masking.enable) /
334 sizeof(unsigned long),
335 .supported = kvm_sbi_fwft_pointer_masking_pmlen_supported,
336 .reset = kvm_sbi_fwft_reset_pointer_masking_pmlen,
337 .set = kvm_sbi_fwft_set_pointer_masking_pmlen,
338 .get = kvm_sbi_fwft_get_pointer_masking_pmlen,
339 },
340 #endif
341 {
342 .id = SBI_FWFT_LANDING_PAD,
343 .first_reg_num = offsetof(struct kvm_riscv_sbi_fwft, landing_pad.enable) /
344 sizeof(unsigned long),
> 345 .supported = kvm_sbi_fwft_landing_pad_supported,
> 346 .reset = kvm_sbi_fwft_reset_landing_pad,
> 347 .set = kvm_sbi_fwft_set_landing_pad,
> 348 .get = kvm_sbi_fwft_get_landing_pad,
349 },
350 {
351 .id = SBI_FWFT_SHADOW_STACK,
352 .first_reg_num = offsetof(struct kvm_riscv_sbi_fwft, shadow_stack.enable) /
353 sizeof(unsigned long),
> 354 .supported = kvm_sbi_fwft_shadow_stack_supported,
> 355 .reset = kvm_sbi_fwft_reset_shadow_stack,
> 356 .set = kvm_sbi_fwft_set_shadow_stack,
> 357 .get = kvm_sbi_fwft_get_shadow_stack,
358 },
359 {
360 .id = SBI_FWFT_PTE_AD_HW_UPDATING,
361 .first_reg_num = offsetof(struct kvm_riscv_sbi_fwft, pte_ad_hw_updating.enable) /
362 sizeof(unsigned long),
> 363 .supported = kvm_sbi_fwft_pte_ad_hw_updating_supported,
> 364 .reset = kvm_sbi_fwft_reset_pte_ad_hw_updating,
> 365 .set = kvm_sbi_fwft_set_pte_ad_hw_updating,
> 366 .get = kvm_sbi_fwft_get_pte_ad_hw_updating,
367 },
368 };
369
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
--
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http://lists.infradead.org/mailman/listinfo/kvm-riscv
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/4] RISC-V: KVM: Allow zicfiss/zicfilp exts for Guest/VM
2025-12-01 1:28 ` [PATCH 1/4] RISC-V: KVM: Allow zicfiss/zicfilp exts for Guest/VM zhouquan
@ 2025-12-03 17:19 ` Deepak Gupta
2025-12-03 17:25 ` Deepak Gupta
2025-12-08 9:53 ` Quan Zhou
0 siblings, 2 replies; 9+ messages in thread
From: Deepak Gupta @ 2025-12-03 17:19 UTC (permalink / raw)
To: zhouquan
Cc: anup, ajones, atishp, paul.walmsley, palmer, linux-kernel,
linux-riscv, kvm, kvm-riscv
On Mon, Dec 01, 2025 at 09:28:25AM +0800, zhouquan@iscas.ac.cn wrote:
>From: Quan Zhou <zhouquan@iscas.ac.cn>
>
>Extend the KVM ISA extension ONE_REG interface to allow KVM user
>space to detect and enable zicfiss/zicfilp exts for Guest/VM,
>the rules defined in the spec [1] are as follows:
>---
>1) Zicfiss extension introduces the SSE field (bit 3) in henvcfg.
>If the SSE field is set to 1, the Zicfiss extension is activated
>in VS-mode. When the SSE field is 0, the Zicfiss extension remains
>inactive in VS-mode.
>
>2) Zicfilp extension introduces the LPE field (bit 2) in henvcfg.
>When the LPE field is set to 1, the Zicfilp extension is enabled
>in VS-mode. When the LPE field is 0, the Zicfilp extension is not
>enabled in VS-mode.
>
>[1] - https://github.com/riscv/riscv-cfi
>
>Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn>
>---
> arch/riscv/include/uapi/asm/kvm.h | 2 ++
> arch/riscv/kvm/vcpu.c | 6 ++++++
> arch/riscv/kvm/vcpu_onereg.c | 2 ++
> 3 files changed, 10 insertions(+)
>
>diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
>index 759a4852c09a..7ca087848a43 100644
>--- a/arch/riscv/include/uapi/asm/kvm.h
>+++ b/arch/riscv/include/uapi/asm/kvm.h
>@@ -190,6 +190,8 @@ enum KVM_RISCV_ISA_EXT_ID {
> KVM_RISCV_ISA_EXT_ZFBFMIN,
> KVM_RISCV_ISA_EXT_ZVFBFMIN,
> KVM_RISCV_ISA_EXT_ZVFBFWMA,
>+ KVM_RISCV_ISA_EXT_ZICFILP,
>+ KVM_RISCV_ISA_EXT_ZICFISS,
> KVM_RISCV_ISA_EXT_MAX,
> };
>
>diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
>index 5ce35aba6069..098d77f9a886 100644
>--- a/arch/riscv/kvm/vcpu.c
>+++ b/arch/riscv/kvm/vcpu.c
>@@ -557,6 +557,12 @@ static void kvm_riscv_vcpu_setup_config(struct kvm_vcpu *vcpu)
> if (riscv_isa_extension_available(isa, ZICBOZ))
> cfg->henvcfg |= ENVCFG_CBZE;
>
>+ if (riscv_isa_extension_available(isa, ZICFILP))
>+ cfg->henvcfg |= ENVCFG_LPE;
Blindly enabling landing pad enforcement on guest kernel will lead to issues
(a guest kernel might not be ready and compiled with landing pad enforcement).
It must be done via a SSE interface where enable is requested by guest kernel.
>+
>+ if (riscv_isa_extension_available(isa, ZICFISS))
>+ cfg->henvcfg |= ENVCFG_SSE;
Same comment on shadow stack enable. While usually shadow stack usage is optin
where explicityl sspush/sspopchk/ssamoswap has to be part of codegen to use the
extension and not modifying existing instruction behavior (like zicfilp does on
`jalr`)
There is a situaion during early boot of kernel where shadow stack permissions
for init shadow stack might not have been configured (or satp == BARE at that
time), in those cases `sspush/sspopchk` in guest kernel will start faulting.
So enabling shadow stack should also be done via SSE interface.
That's how user cfi patchsets also do.
>+
> if (riscv_isa_extension_available(isa, SVADU) &&
> !riscv_isa_extension_available(isa, SVADE))
> cfg->henvcfg |= ENVCFG_ADUE;
>diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c
>index 865dae903aa0..3d05a4bafd9b 100644
>--- a/arch/riscv/kvm/vcpu_onereg.c
>+++ b/arch/riscv/kvm/vcpu_onereg.c
>@@ -72,6 +72,8 @@ static const unsigned long kvm_isa_ext_arr[] = {
> KVM_ISA_EXT_ARR(ZICBOP),
> KVM_ISA_EXT_ARR(ZICBOZ),
> KVM_ISA_EXT_ARR(ZICCRSE),
>+ KVM_ISA_EXT_ARR(ZICFILP),
>+ KVM_ISA_EXT_ARR(ZICFISS),
> KVM_ISA_EXT_ARR(ZICNTR),
> KVM_ISA_EXT_ARR(ZICOND),
> KVM_ISA_EXT_ARR(ZICSR),
>--
>2.34.1
>
>
--
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/4] RISC-V: KVM: Allow zicfiss/zicfilp exts for Guest/VM
2025-12-03 17:19 ` Deepak Gupta
@ 2025-12-03 17:25 ` Deepak Gupta
2025-12-08 9:53 ` Quan Zhou
1 sibling, 0 replies; 9+ messages in thread
From: Deepak Gupta @ 2025-12-03 17:25 UTC (permalink / raw)
To: zhouquan
Cc: anup, ajones, atishp, paul.walmsley, palmer, linux-kernel,
linux-riscv, kvm, kvm-riscv
On Wed, Dec 03, 2025 at 09:19:28AM -0800, Deepak Gupta wrote:
>On Mon, Dec 01, 2025 at 09:28:25AM +0800, zhouquan@iscas.ac.cn wrote:
>>From: Quan Zhou <zhouquan@iscas.ac.cn>
>>
>>Extend the KVM ISA extension ONE_REG interface to allow KVM user
>>space to detect and enable zicfiss/zicfilp exts for Guest/VM,
>>the rules defined in the spec [1] are as follows:
>>---
>>1) Zicfiss extension introduces the SSE field (bit 3) in henvcfg.
>>If the SSE field is set to 1, the Zicfiss extension is activated
>>in VS-mode. When the SSE field is 0, the Zicfiss extension remains
>>inactive in VS-mode.
>>
>>2) Zicfilp extension introduces the LPE field (bit 2) in henvcfg.
>>When the LPE field is set to 1, the Zicfilp extension is enabled
>>in VS-mode. When the LPE field is 0, the Zicfilp extension is not
>>enabled in VS-mode.
>>
>>[1] - https://github.com/riscv/riscv-cfi
>>
>>Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn>
>>---
>>arch/riscv/include/uapi/asm/kvm.h | 2 ++
>>arch/riscv/kvm/vcpu.c | 6 ++++++
>>arch/riscv/kvm/vcpu_onereg.c | 2 ++
>>3 files changed, 10 insertions(+)
>>
>>diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
>>index 759a4852c09a..7ca087848a43 100644
>>--- a/arch/riscv/include/uapi/asm/kvm.h
>>+++ b/arch/riscv/include/uapi/asm/kvm.h
>>@@ -190,6 +190,8 @@ enum KVM_RISCV_ISA_EXT_ID {
>> KVM_RISCV_ISA_EXT_ZFBFMIN,
>> KVM_RISCV_ISA_EXT_ZVFBFMIN,
>> KVM_RISCV_ISA_EXT_ZVFBFWMA,
>>+ KVM_RISCV_ISA_EXT_ZICFILP,
>>+ KVM_RISCV_ISA_EXT_ZICFISS,
>> KVM_RISCV_ISA_EXT_MAX,
>>};
>>
>>diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
>>index 5ce35aba6069..098d77f9a886 100644
>>--- a/arch/riscv/kvm/vcpu.c
>>+++ b/arch/riscv/kvm/vcpu.c
>>@@ -557,6 +557,12 @@ static void kvm_riscv_vcpu_setup_config(struct kvm_vcpu *vcpu)
>> if (riscv_isa_extension_available(isa, ZICBOZ))
>> cfg->henvcfg |= ENVCFG_CBZE;
>>
>>+ if (riscv_isa_extension_available(isa, ZICFILP))
>>+ cfg->henvcfg |= ENVCFG_LPE;
>
>Blindly enabling landing pad enforcement on guest kernel will lead to issues
>(a guest kernel might not be ready and compiled with landing pad enforcement).
>It must be done via a SSE interface where enable is requested by guest kernel.
>
>>+
>>+ if (riscv_isa_extension_available(isa, ZICFISS))
>>+ cfg->henvcfg |= ENVCFG_SSE;
>
>Same comment on shadow stack enable. While usually shadow stack usage is optin
>where explicityl sspush/sspopchk/ssamoswap has to be part of codegen to use the
>extension and not modifying existing instruction behavior (like zicfilp does on
>`jalr`)
>There is a situaion during early boot of kernel where shadow stack permissions
>for init shadow stack might not have been configured (or satp == BARE at that
>time), in those cases `sspush/sspopchk` in guest kernel will start faulting.
>
>So enabling shadow stack should also be done via SSE interface.
I meant FWFT (not SSE), sorry.
>
>That's how user cfi patchsets also do.
>
>>+
>> if (riscv_isa_extension_available(isa, SVADU) &&
>> !riscv_isa_extension_available(isa, SVADE))
>> cfg->henvcfg |= ENVCFG_ADUE;
>>diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c
>>index 865dae903aa0..3d05a4bafd9b 100644
>>--- a/arch/riscv/kvm/vcpu_onereg.c
>>+++ b/arch/riscv/kvm/vcpu_onereg.c
>>@@ -72,6 +72,8 @@ static const unsigned long kvm_isa_ext_arr[] = {
>> KVM_ISA_EXT_ARR(ZICBOP),
>> KVM_ISA_EXT_ARR(ZICBOZ),
>> KVM_ISA_EXT_ARR(ZICCRSE),
>>+ KVM_ISA_EXT_ARR(ZICFILP),
>>+ KVM_ISA_EXT_ARR(ZICFISS),
>> KVM_ISA_EXT_ARR(ZICNTR),
>> KVM_ISA_EXT_ARR(ZICOND),
>> KVM_ISA_EXT_ARR(ZICSR),
>>--
>>2.34.1
>>
>>
--
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/4] RISC-V: KVM: Allow zicfiss/zicfilp exts for Guest/VM
2025-12-03 17:19 ` Deepak Gupta
2025-12-03 17:25 ` Deepak Gupta
@ 2025-12-08 9:53 ` Quan Zhou
1 sibling, 0 replies; 9+ messages in thread
From: Quan Zhou @ 2025-12-08 9:53 UTC (permalink / raw)
To: Deepak Gupta
Cc: anup, ajones, atishp, paul.walmsley, palmer, linux-kernel,
linux-riscv, kvm, kvm-riscv
On 2025/12/4 01:19, Deepak Gupta wrote:
> On Mon, Dec 01, 2025 at 09:28:25AM +0800, zhouquan@iscas.ac.cn wrote:
>> From: Quan Zhou <zhouquan@iscas.ac.cn>
>>
>> Extend the KVM ISA extension ONE_REG interface to allow KVM user
>> space to detect and enable zicfiss/zicfilp exts for Guest/VM,
>> the rules defined in the spec [1] are as follows:
>> ---
>> 1) Zicfiss extension introduces the SSE field (bit 3) in henvcfg.
>> If the SSE field is set to 1, the Zicfiss extension is activated
>> in VS-mode. When the SSE field is 0, the Zicfiss extension remains
>> inactive in VS-mode.
>>
>> 2) Zicfilp extension introduces the LPE field (bit 2) in henvcfg.
>> When the LPE field is set to 1, the Zicfilp extension is enabled
>> in VS-mode. When the LPE field is 0, the Zicfilp extension is not
>> enabled in VS-mode.
>>
>> [1] - https://github.com/riscv/riscv-cfi
>>
>> Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn>
>> ---
>> arch/riscv/include/uapi/asm/kvm.h | 2 ++
>> arch/riscv/kvm/vcpu.c | 6 ++++++
>> arch/riscv/kvm/vcpu_onereg.c | 2 ++
>> 3 files changed, 10 insertions(+)
>>
>> diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/
>> uapi/asm/kvm.h
>> index 759a4852c09a..7ca087848a43 100644
>> --- a/arch/riscv/include/uapi/asm/kvm.h
>> +++ b/arch/riscv/include/uapi/asm/kvm.h
>> @@ -190,6 +190,8 @@ enum KVM_RISCV_ISA_EXT_ID {
>> KVM_RISCV_ISA_EXT_ZFBFMIN,
>> KVM_RISCV_ISA_EXT_ZVFBFMIN,
>> KVM_RISCV_ISA_EXT_ZVFBFWMA,
>> + KVM_RISCV_ISA_EXT_ZICFILP,
>> + KVM_RISCV_ISA_EXT_ZICFISS,
>> KVM_RISCV_ISA_EXT_MAX,
>> };
>>
>> diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
>> index 5ce35aba6069..098d77f9a886 100644
>> --- a/arch/riscv/kvm/vcpu.c
>> +++ b/arch/riscv/kvm/vcpu.c
>> @@ -557,6 +557,12 @@ static void kvm_riscv_vcpu_setup_config(struct
>> kvm_vcpu *vcpu)
>> if (riscv_isa_extension_available(isa, ZICBOZ))
>> cfg->henvcfg |= ENVCFG_CBZE;
>>
>> + if (riscv_isa_extension_available(isa, ZICFILP))
>> + cfg->henvcfg |= ENVCFG_LPE;
>
> Blindly enabling landing pad enforcement on guest kernel will lead to
> issues
> (a guest kernel might not be ready and compiled with landing pad
> enforcement).
> It must be done via a SSE interface where enable is requested by guest
> kernel.
>
>> +
>> + if (riscv_isa_extension_available(isa, ZICFISS))
>> + cfg->henvcfg |= ENVCFG_SSE;
>
> Same comment on shadow stack enable. While usually shadow stack usage is
> optin
> where explicityl sspush/sspopchk/ssamoswap has to be part of codegen to
> use the
> extension and not modifying existing instruction behavior (like zicfilp
> does on
> `jalr`)
> There is a situaion during early boot of kernel where shadow stack
> permissions
> for init shadow stack might not have been configured (or satp == BARE at
> that
> time), in those cases `sspush/sspopchk` in guest kernel will start
> faulting.
>
> So enabling shadow stack should also be done via SSE interface.
>
> That's how user cfi patchsets also do.
>
Okay, I will fix it.
Thanks,
Quan
>> +
>> if (riscv_isa_extension_available(isa, SVADU) &&
>> !riscv_isa_extension_available(isa, SVADE))
>> cfg->henvcfg |= ENVCFG_ADUE;
>> diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c
>> index 865dae903aa0..3d05a4bafd9b 100644
>> --- a/arch/riscv/kvm/vcpu_onereg.c
>> +++ b/arch/riscv/kvm/vcpu_onereg.c
>> @@ -72,6 +72,8 @@ static const unsigned long kvm_isa_ext_arr[] = {
>> KVM_ISA_EXT_ARR(ZICBOP),
>> KVM_ISA_EXT_ARR(ZICBOZ),
>> KVM_ISA_EXT_ARR(ZICCRSE),
>> + KVM_ISA_EXT_ARR(ZICFILP),
>> + KVM_ISA_EXT_ARR(ZICFISS),
>> KVM_ISA_EXT_ARR(ZICNTR),
>> KVM_ISA_EXT_ARR(ZICOND),
>> KVM_ISA_EXT_ARR(ZICSR),
>> --
>> 2.34.1
>>
>>
--
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^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2025-12-08 10:10 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-12-01 1:28 [PATCH 0/4] RISC-V: KVM: Add Zicfiss/Zicfilp support zhouquan
2025-12-01 1:28 ` [PATCH 1/4] RISC-V: KVM: Allow zicfiss/zicfilp exts for Guest/VM zhouquan
2025-12-03 17:19 ` Deepak Gupta
2025-12-03 17:25 ` Deepak Gupta
2025-12-08 9:53 ` Quan Zhou
2025-12-01 1:28 ` [PATCH 2/4] RISC-V: KVM: Add support for software check exception zhouquan
2025-12-01 1:28 ` [PATCH 3/4] RISC-V: KVM: Add suuport for zicfiss/zicfilp/svadu FWFT features zhouquan
2025-12-03 10:52 ` kernel test robot
2025-12-01 1:29 ` [PATCH 4/4] KVM: riscv: selftests: Add zicfiss/zicfilp/svadu and SBI FWFT to get-reg-list test zhouquan
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