From mboxrd@z Thu Jan 1 00:00:00 1970 From: Min-gyu Kim Subject: RE: [PATCH v9 13/16] ARM: KVM: Emulation framework and CP15 emulation Date: Tue, 17 Jul 2012 19:54:20 +0900 Message-ID: <000601cd640a$855679e0$90036da0$@samsung.com> References: <20120703085841.27746.82730.stgit@ubuntu> <20120703090138.27746.22965.stgit@ubuntu> <000001cd5ff0$24a1b6a0$6de523e0$@samsung.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Cc: android-virt@lists.cs.columbia.edu, kvm@vger.kernel.org, tech@virtualopensystems.com, =?UTF-8?B?J+q5gOywve2ZmCc=?= To: 'Christoffer Dall' Return-path: Received: from mailout1.samsung.com ([203.254.224.24]:34900 "EHLO mailout1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751466Ab2GQKym convert rfc822-to-8bit (ORCPT ); Tue, 17 Jul 2012 06:54:42 -0400 Received: from epcpsbgm2.samsung.com (mailout1.samsung.com [203.254.224.24]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M7A0048HWYLQBM0@mailout1.samsung.com> for kvm@vger.kernel.org; Tue, 17 Jul 2012 19:54:22 +0900 (KST) Received: from MingyuPC ([182.198.1.3]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M7A00L5KWYLFQ50@mmp2.samsung.com> for kvm@vger.kernel.org; Tue, 17 Jul 2012 19:54:21 +0900 (KST) In-reply-to: Content-language: ko Sender: kvm-owner@vger.kernel.org List-ID: Why does the cache operation need to happen on the same CPU while the L1 caches between cores are coherent? As you know, cache operations usually operate for a range and it iterates without disabling preemption. Therefore, though you enclose the vcpu_run and handle_exit with preemption disable, the operations on a range can run on several cores. If data of address X is written from CPU0 and CPU1 executes cache flush on address X while those 2 CPUs have same TTBR, does the cache operation fail? It seems to succeed from the document from ARM that I referred before. And that's why I think the preemption disable is unnecessary. Regards Kim, Min-gyu -----Original Message----- > And you said the reason of disabling preemption as CPU-specific data such as caches. > But as far as I know, the l1 caches are coherent. > (http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0438e/ > BABFHDFE.html) > > Can you please explain why preemption disable is necessary in detail? > if a VM tries to do a cache maintenance operation specific to that CPU that traps we want to make sure that the emulation of such operations happen on the same physical CPU to ensure correct semantics. -Christoffer