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Tue, 21 Oct 2025 10:35:25 GMT Received: from smtpav02.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3D6825805C; Tue, 21 Oct 2025 10:35:37 +0000 (GMT) Received: from smtpav02.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C15345805F; Tue, 21 Oct 2025 10:35:34 +0000 (GMT) Received: from [9.79.201.141] (unknown [9.79.201.141]) by smtpav02.dal12v.mail.ibm.com (Postfix) with ESMTPS; Tue, 21 Oct 2025 10:35:34 +0000 (GMT) Message-ID: <003640ee-8bd6-4366-b9eb-841c671bbf93@linux.ibm.com> Date: Tue, 21 Oct 2025 16:05:32 +0530 Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 02/11] hw/ppc/spapr: Remove SpaprMachineClass::nr_xirqs field To: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Nicholas Piggin , kvm@vger.kernel.org, Paolo Bonzini , Harsh Prateek Bora , =?UTF-8?Q?C=C3=A9dric_Le_Goater?= References: <20251021084346.73671-1-philmd@linaro.org> <20251021084346.73671-3-philmd@linaro.org> Content-Language: en-US From: Chinmay Rath In-Reply-To: <20251021084346.73671-3-philmd@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-Authority-Analysis: v=2.4 cv=FMYWBuos c=1 sm=1 tr=0 ts=68f761fb cx=c_pps a=3Bg1Hr4SwmMryq2xdFQyZA==:117 a=3Bg1Hr4SwmMryq2xdFQyZA==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=KKAkSRfTAAAA:8 a=E3IZGcUWJODU3JGwBZgA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=cvBusfyB2V15izCimMoJ:22 a=HhbK4dLum7pmb74im6QT:22 a=cPQSjfK2_nFv0Q5t_7PE:22 a=pHzHmUro8NiASowvMSCR:22 a=Ew2E2A-JSTLzCXPT_086:22 X-Proofpoint-GUID: j7Rch_yy3CGt35pD3RIwzm29faEQDqPx X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDE4MDAyMiBTYWx0ZWRfX1H0M0HH5d3UD zCUpykDAXfpbwtpo9QUoFbp9w0wYvLJcmln772XmMRsJgvB2zis6UlDlAjAwJXTzC5I8gI2vFtm MFd7cUi9lo/kinDR9veMP6t9JvD6G+VRcHv/EOBtyTloPi4s4GpWc7Rqh5+3OeYHsuFzdGEDrKH UNce58FW1BbPDqmG2eHMiT+frHCEi7MyOTHBeUNWfOTri1hKWWJ6Olvrel0L0AzbUgVKWcyrI1R IE93U7I/yq3yV1CJaWkN1MaVVPCnIMViv7dbIeOlfNQgX2WfVpJhVCXF0I5fzey5MrTOa9JZrm3 UIobfd9iH1vzlrIf+Cjt71oy2qA6lDjzHxjvdq89CZYYDEQ3Kw/jCs5GNBeQEt3+Psmoh4tEQhN DsVK5VgwRVHyKsWD+ngr1l6ADjJ38A== X-Proofpoint-ORIG-GUID: p36Pj74-xOpFNMmX3qz_Aq_ACeNhUSkA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-20_07,2025-10-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1011 impostorscore=0 priorityscore=1501 adultscore=0 bulkscore=0 lowpriorityscore=0 suspectscore=0 phishscore=0 spamscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510020000 definitions=main-2510180022 On 10/21/25 14:13, Philippe Mathieu-Daudé wrote: > The SpaprMachineClass::nr_xirqs field was only used by the > pseries-3.0 machine, which got removed. Remove it as now unused. > > Signed-off-by: Philippe Mathieu-Daudé > --- > include/hw/ppc/spapr.h | 1 - > hw/ppc/spapr.c | 1 - > hw/ppc/spapr_irq.c | 22 +++++++--------------- > 3 files changed, 7 insertions(+), 17 deletions(-) > > diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h > index 0c1e5132de2..494367fb99a 100644 > --- a/include/hw/ppc/spapr.h > +++ b/include/hw/ppc/spapr.h > @@ -145,7 +145,6 @@ struct SpaprMachineClass { > /*< public >*/ > bool dr_phb_enabled; /* enable dynamic-reconfig/hotplug of PHBs */ > bool update_dt_enabled; /* enable KVMPPC_H_UPDATE_DT */ > - uint32_t nr_xirqs; > bool broken_host_serial_model; /* present real host info to the guest */ > bool pre_4_1_migration; /* don't migrate hpt-max-page-size */ > bool linux_pci_probe; > diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c > index 426a778d3e8..b5d20bc1756 100644 > --- a/hw/ppc/spapr.c > +++ b/hw/ppc/spapr.c > @@ -4691,7 +4691,6 @@ static void spapr_machine_class_init(ObjectClass *oc, const void *data) > smc->dr_phb_enabled = true; > smc->linux_pci_probe = true; > smc->smp_threads_vsmt = true; > - smc->nr_xirqs = SPAPR_NR_XIRQS; > xfc->match_nvt = spapr_match_nvt; > vmc->client_architecture_support = spapr_vof_client_architecture_support; > vmc->quiesce = spapr_vof_quiesce; > diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c > index 317d57a3802..2ce323457be 100644 > --- a/hw/ppc/spapr_irq.c > +++ b/hw/ppc/spapr_irq.c > @@ -279,15 +279,11 @@ void spapr_irq_dt(SpaprMachineState *spapr, uint32_t nr_servers, > > uint32_t spapr_irq_nr_msis(SpaprMachineState *spapr) > { > - SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); > - > - return SPAPR_XIRQ_BASE + smc->nr_xirqs - SPAPR_IRQ_MSI; > + return SPAPR_NR_XIRQS + SPAPR_XIRQ_BASE - SPAPR_IRQ_MSI; > } Hey, With this cleanup, I think we can get rid of the SpaprMachineState argument passed to spapr_irq_nr_msis function since it is not used anymore ^. Regards, Chinmay > > void spapr_irq_init(SpaprMachineState *spapr, Error **errp) > { > - SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); > - > if (kvm_enabled() && kvm_kernel_irqchip_split()) { > error_setg(errp, "kernel_irqchip split mode not supported on pseries"); > return; > @@ -308,7 +304,7 @@ void spapr_irq_init(SpaprMachineState *spapr, Error **errp) > object_property_add_child(OBJECT(spapr), "ics", obj); > object_property_set_link(obj, ICS_PROP_XICS, OBJECT(spapr), > &error_abort); > - object_property_set_int(obj, "nr-irqs", smc->nr_xirqs, &error_abort); > + object_property_set_int(obj, "nr-irqs", SPAPR_NR_XIRQS, &error_abort); > if (!qdev_realize(DEVICE(obj), NULL, errp)) { > return; > } > @@ -322,7 +318,7 @@ void spapr_irq_init(SpaprMachineState *spapr, Error **errp) > int i; > > dev = qdev_new(TYPE_SPAPR_XIVE); > - qdev_prop_set_uint32(dev, "nr-irqs", smc->nr_xirqs + SPAPR_IRQ_NR_IPIS); > + qdev_prop_set_uint32(dev, "nr-irqs", SPAPR_NR_XIRQS + SPAPR_IRQ_NR_IPIS); > /* > * 8 XIVE END structures per CPU. One for each available > * priority > @@ -349,7 +345,7 @@ void spapr_irq_init(SpaprMachineState *spapr, Error **errp) > } > > spapr->qirqs = qemu_allocate_irqs(spapr_set_irq, spapr, > - smc->nr_xirqs + SPAPR_IRQ_NR_IPIS); > + SPAPR_NR_XIRQS + SPAPR_IRQ_NR_IPIS); > > /* > * Mostly we don't actually need this until reset, except that not > @@ -364,11 +360,10 @@ int spapr_irq_claim(SpaprMachineState *spapr, int irq, bool lsi, Error **errp) > { > SpaprInterruptController *intcs[] = ALL_INTCS(spapr); > int i; > - SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); > int rc; > > assert(irq >= SPAPR_XIRQ_BASE); > - assert(irq < (smc->nr_xirqs + SPAPR_XIRQ_BASE)); > + assert(irq < (SPAPR_NR_XIRQS + SPAPR_XIRQ_BASE)); > > for (i = 0; i < ARRAY_SIZE(intcs); i++) { > SpaprInterruptController *intc = intcs[i]; > @@ -388,10 +383,9 @@ void spapr_irq_free(SpaprMachineState *spapr, int irq, int num) > { > SpaprInterruptController *intcs[] = ALL_INTCS(spapr); > int i, j; > - SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); > > assert(irq >= SPAPR_XIRQ_BASE); > - assert((irq + num) <= (smc->nr_xirqs + SPAPR_XIRQ_BASE)); > + assert((irq + num) <= (SPAPR_NR_XIRQS + SPAPR_XIRQ_BASE)); > > for (i = irq; i < (irq + num); i++) { > for (j = 0; j < ARRAY_SIZE(intcs); j++) { > @@ -408,8 +402,6 @@ void spapr_irq_free(SpaprMachineState *spapr, int irq, int num) > > qemu_irq spapr_qirq(SpaprMachineState *spapr, int irq) > { > - SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); > - > /* > * This interface is basically for VIO and PHB devices to find the > * right qemu_irq to manipulate, so we only allow access to the > @@ -418,7 +410,7 @@ qemu_irq spapr_qirq(SpaprMachineState *spapr, int irq) > * interfaces, we can change this if we need to in future. > */ > assert(irq >= SPAPR_XIRQ_BASE); > - assert(irq < (smc->nr_xirqs + SPAPR_XIRQ_BASE)); > + assert(irq < (SPAPR_NR_XIRQS + SPAPR_XIRQ_BASE)); > > if (spapr->ics) { > assert(ics_valid_irq(spapr->ics, irq));