From: "Edgecombe, Rick P" <rick.p.edgecombe@intel.com>
To: "seanjc@google.com" <seanjc@google.com>
Cc: "kvm@vger.kernel.org" <kvm@vger.kernel.org>,
"dave.hansen@linux.intel.com" <dave.hansen@linux.intel.com>,
"thomas.lendacky@amd.com" <thomas.lendacky@amd.com>,
"dionnaglaze@google.com" <dionnaglaze@google.com>,
"Wu, Binbin" <binbin.wu@intel.com>,
"kirill.shutemov@linux.intel.com"
<kirill.shutemov@linux.intel.com>,
"mingo@redhat.com" <mingo@redhat.com>,
"pbonzini@redhat.com" <pbonzini@redhat.com>,
"tglx@linutronix.de" <tglx@linutronix.de>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"hpa@zytor.com" <hpa@zytor.com>,
"vkuznets@redhat.com" <vkuznets@redhat.com>,
"bp@alien8.de" <bp@alien8.de>,
"jgross@suse.com" <jgross@suse.com>,
"pgonda@google.com" <pgonda@google.com>,
"x86@kernel.org" <x86@kernel.org>
Subject: Re: [PATCH 0/2] x86/kvm: Force legacy PCI hole as WB under SNP/TDX
Date: Mon, 3 Feb 2025 23:01:10 +0000 [thread overview]
Message-ID: <0102090cd553e42709f43c30d2982b2c713e1a68.camel@intel.com> (raw)
In-Reply-To: <Z6EoAAHn4d_FujZa@google.com>
On Mon, 2025-02-03 at 12:33 -0800, Sean Christopherson wrote:
> > Since there is no upstream KVM TDX support yet, why isn't it an option to
> > still
> > revert the EDKII commit too? It was a relatively recent change.
>
> I'm fine with that route too, but it too is a band-aid. Relying on the
> *untrusted*
> hypervisor to essentially communicate memory maps is not a winning strategy.
>
> > To me it seems that the normal KVM MTRR support is not ideal, because it is
> > still lying about what it is doing. For example, in the past there was an
> > attempt to use UC to prevent speculative execution accesses to sensitive
> > data.
> > The KVM MTRR support only happens to work with existing guests, but not all
> > possible MTRR usages.
> >
> > Since diverging from the architecture creates loose ends like that, we could
> > instead define some other way for EDKII to communicate the ranges to the
> > kernel.
> > Like some simple KVM PV MSRs that are for communication only, and not
>
> Hard "no" to any PV solution. This isn't KVM specific, and as above, bouncing
> through the hypervisor to communicate information within the guest is asinine,
> especially for CoCo VMs.
Hmm, right.
So the other options could be:
1. Some TDX module feature to hold the ranges:
- Con: Not shared with AMD
2. Re-use MTRRs for the communication, revert changes in guest and edk2:
- Con: Creating more half support, when it's technically not required
- Con: Still bouncing through the hypervisor
- Pro: Design and code is clear
3. Create some new architectural definition, like a bit that means "MTRRs don't
actually work:
- Con: Takes a long time, need to get agreement
- Con: Still bouncing through the hypervisor
- Pro: More pure solution
4. Do this series:
- Pro: Looks ok to me
- Cons: As explained in the patches, it's a bit hacky.
- Cons: Could there be more cases than the legacy PCI hole?
I would kind of like to see something like 3, but 2 or 4 seem the only feasible
ones if we want to resolve this soon.
next prev parent reply other threads:[~2025-02-03 23:01 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-01 0:50 [PATCH 0/2] x86/kvm: Force legacy PCI hole as WB under SNP/TDX Sean Christopherson
2025-02-01 0:50 ` [PATCH 1/2] x86/mtrr: Return success vs. "failure" from guest_force_mtrr_state() Sean Christopherson
2025-02-01 0:50 ` [PATCH 2/2] x86/kvm: Override low memory above TOLUD to WB when MTRRs are forced WB Sean Christopherson
2025-02-01 14:25 ` [PATCH 0/2] x86/kvm: Force legacy PCI hole as WB under SNP/TDX Dionna Amalie Glaze
2025-02-03 18:14 ` Edgecombe, Rick P
2025-02-03 20:33 ` Sean Christopherson
2025-02-03 23:01 ` Edgecombe, Rick P [this message]
2025-02-04 0:27 ` Sean Christopherson
2025-02-05 3:51 ` Edgecombe, Rick P
2025-02-05 7:49 ` Xu, Min M
2025-02-10 15:29 ` Binbin Wu
2025-07-08 14:24 ` Nikolay Borisov
-- strict thread matches above, loose matches on Subject: below --
2025-07-09 16:54 Jianxiong Gao
2025-07-14 9:06 ` Binbin Wu
2025-07-14 11:24 ` Nikolay Borisov
2025-07-15 2:53 ` Binbin Wu
2025-07-16 9:51 ` Binbin Wu
2025-07-23 14:34 ` Sean Christopherson
2025-07-24 3:16 ` Binbin Wu
2025-07-28 15:33 ` Sean Christopherson
2025-07-30 7:34 ` Binbin Wu
2025-08-15 23:55 ` Korakit Seemakhupt
2025-08-18 11:07 ` Binbin Wu
2025-08-20 3:07 ` Vishal Annapurve
2025-08-20 10:03 ` Binbin Wu
2025-08-20 11:13 ` Binbin Wu
2025-08-20 17:56 ` Sean Christopherson
2025-08-21 3:30 ` Binbin Wu
2025-08-21 5:23 ` Binbin Wu
2025-08-21 6:02 ` Jürgen Groß
2025-08-21 15:27 ` Sean Christopherson
2025-08-28 0:07 ` Sean Christopherson
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