From: Xiaoyao Li <xiaoyao.li@intel.com>
To: "Sohil Mehta" <sohil.mehta@intel.com>,
"David Woodhouse" <dwmw2@infradead.org>,
x86@kernel.org, "Dave Hansen" <dave.hansen@linux.intel.com>,
"Tony Luck" <tony.luck@intel.com>,
"Jürgen Gross" <jgross@suse.com>,
"Boris Ostrovsky" <boris.ostrovsky@oracle.com>,
xen-devel <xen-devel@lists.xenproject.org>
Cc: Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Namhyung Kim <namhyung@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@kernel.org>, Ian Rogers <irogers@google.com>,
Adrian Hunter <adrian.hunter@intel.com>,
Kan Liang <kan.liang@linux.intel.com>,
Thomas Gleixner <tglx@linutronix.de>,
Borislav Petkov <bp@alien8.de>, "H . Peter Anvin" <hpa@zytor.com>,
"Rafael J . Wysocki" <rafael@kernel.org>,
Len Brown <lenb@kernel.org>, Andy Lutomirski <luto@kernel.org>,
Viresh Kumar <viresh.kumar@linaro.org>,
Jean Delvare <jdelvare@suse.com>,
Guenter Roeck <linux@roeck-us.net>,
Zhang Rui <rui.zhang@intel.com>,
Andrew Cooper <andrew.cooper3@citrix.com>,
David Laight <david.laight.linux@gmail.com>,
Dapeng Mi <dapeng1.mi@linux.intel.com>,
linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-acpi@vger.kernel.org, linux-pm@vger.kernel.org,
kvm@vger.kernel.org, Xin Li <xin@zytor.com>
Subject: Re: [PATCH v3 13/15] x86/cpu/intel: Bound the non-architectural constant_tsc model checks
Date: Fri, 22 Aug 2025 09:46:48 +0800 [thread overview]
Message-ID: <03ac8bac-c8d1-4a3b-a07f-2bbf04e726b6@intel.com> (raw)
In-Reply-To: <5f5f1230-f373-469c-b0d9-abc80199886e@intel.com>
On 8/22/2025 3:43 AM, Sohil Mehta wrote:
> On 8/21/2025 12:34 PM, Sohil Mehta wrote:
>> On 8/21/2025 6:15 AM, David Woodhouse wrote:
>>
>>> Hm. My test host is INTEL_HASWELL_X (0x63f). For reasons which are
>>> unclear to me, QEMU doesn't set bit 8 of 0x80000007 EDX unless I
>>> explicitly append ',+invtsc' to the existing '-cpu host' on its command
>>> line. So now my guest doesn't think it has X86_FEATURE_CONSTANT_TSC.
>>>
>>
>> Haswell should have X86_FEATURE_CONSTANT_TSC, so I would have expected
>> the guest bit to be set. Until now, X86_FEATURE_CONSTANT_TSC was set
>> based on the Family-model instead of the CPUID enumeration which may
>> have hid the issue.
>>
>
> Correction:
> s/instead/as well as
>
>> From my initial look at the QEMU implementation, this seems intentional.
>>
>> QEMU considers Invariant TSC as un-migratable which prevents it from
>> being exposed to migratable guests (default).
>> target/i386/cpu.c:
>> [FEAT_8000_0007_EDX]
>> .unmigratable_flags = CPUID_APM_INVTSC,
>>
>> Can you please try '-cpu host,migratable=off'?
>
> This is mainly to verify. If confirmed, I am not sure what the long term
> solution should be.
yeah. It's the intentional behavior of QEMU.
Invariant TSC is ummigratable unless users explicitly configures the TSC
frequency, e.g., "-cpu host,tsc-frequency=xxx". Because the TSC
frequency is by default the host's frequency if no "tsc-frequency"
specified, and it will change when the VM is migrated to a host with a
different TSC frequency.
It's the specific behavior/rule of QEMU. We just need to keep it in
mind. If we want to expose invariant TSC to the guest with QEMU's "-cpu
host", we can either:
1) explicitly configure the "tsc-frequency", or
2) explicitly turn off "migratable"
next prev parent reply other threads:[~2025-08-22 1:46 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20250219184133.816753-1-sohil.mehta@intel.com>
[not found] ` <20250219184133.816753-14-sohil.mehta@intel.com>
[not found] ` <6f05a6849fb7b22db35216dcf12bf537f8a43a92.camel@infradead.org>
2025-08-21 19:34 ` [PATCH v3 13/15] x86/cpu/intel: Bound the non-architectural constant_tsc model checks Sohil Mehta
2025-08-21 19:43 ` Sohil Mehta
2025-08-21 20:09 ` David Woodhouse
2025-08-22 1:46 ` Xiaoyao Li [this message]
2025-08-24 22:39 ` Demi Marie Obenour
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