Re: [kvm-unit-tests PATCH v2 3/8] arm64: microbench: gic: Add gicv4.1 support for ipi latency test.

[Marc Zyngier <maz@kernel.org>]

Hi Eric,

On 2020-07-02 13:57, Auger Eric wrote:
> Hi Jingyi,
> 
> On 7/2/20 5:01 AM, Jingyi Wang wrote:
>> If gicv4.1(sgi hardware injection) supported, we test ipi injection
>> via hw/sw way separately.
>> 
>> Signed-off-by: Jingyi Wang <wangjingyi11@huawei.com>
>> ---
>>  arm/micro-bench.c    | 45 
>> +++++++++++++++++++++++++++++++++++++++-----
>>  lib/arm/asm/gic-v3.h |  3 +++
>>  lib/arm/asm/gic.h    |  1 +
>>  3 files changed, 44 insertions(+), 5 deletions(-)
>> 
>> diff --git a/arm/micro-bench.c b/arm/micro-bench.c
>> index fc4d356..80d8db3 100644
>> --- a/arm/micro-bench.c
>> +++ b/arm/micro-bench.c
>> @@ -91,9 +91,40 @@ static void gic_prep_common(void)
>>  	assert(irq_ready);
>>  }
>> 
>> -static void ipi_prep(void)
>> +static bool ipi_prep(void)
> Any reason why the bool returned value is preferred over the standard 
> int?
>>  {
>> +	u32 val;
>> +
>> +	val = readl(vgic_dist_base + GICD_CTLR);
>> +	if (readl(vgic_dist_base + GICD_TYPER2) & GICD_TYPER2_nASSGIcap) {
>> +		val &= ~GICD_CTLR_ENABLE_G1A;
>> +		val &= ~GICD_CTLR_nASSGIreq;
>> +		writel(val, vgic_dist_base + GICD_CTLR);
>> +		val |= GICD_CTLR_ENABLE_G1A;
>> +		writel(val, vgic_dist_base + GICD_CTLR);
> Why do we need this G1A dance?

Because it isn't legal to change the SGI behaviour when groups are 
enabled.
Yes, it is described in this bit of documentation nobody has access to.

And this code needs to track RWP on disabling Group-1.

         M.
-- 
Jazz is not dead. It just smells funny...