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From: Paolo Bonzini <pbonzini@redhat.com>
To: Peter Feiner <pfeiner@google.com>
Cc: kvm@vger.kernel.org, David Matlack <dmatlack@google.com>
Subject: Re: [PATCH 4/4] x86: kvm: mmu: use ept a/d in vmcs02 iff used in vmcs12
Date: Sat, 1 Jul 2017 01:29:32 -0400 (EDT)	[thread overview]
Message-ID: <1103545766.13264371.1498886972980.JavaMail.zimbra@redhat.com> (raw)
In-Reply-To: <5bdf824538481ee2308354165e8ebe7b59b7b8a1.1498868316.git.pfeiner@google.com>


> @@ -8358,7 +8349,7 @@ static int vmx_handle_exit(struct kvm_vcpu *vcpu)
>  	 * mode as if vcpus is in root mode, the PML buffer must has been
>  	 * flushed already.
>  	 */
> -	if (enable_pml)
> +	if (enable_pml && !is_guest_mode(vcpu))
>  		vmx_flush_pml_buffer(vcpu);
>  
>  	/* If guest state is invalid, start emulating */

I don't understand this.  You need to flush the PML buffer if
L2 is running with EPT A/D bits enabled, don't you? Apart from
this it seems sane, I only have to look at patch 3 more carefully.

Thanks,

Paolo

  reply	other threads:[~2017-07-01  5:29 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-07-01  0:26 [PATCH 0/4] Fix nested EPT when A/D bits are disabled Peter Feiner
2017-07-01  0:26 ` [PATCH 1/4] x86: kvm: mmu: dead code thanks to access tracking Peter Feiner
2017-07-01  0:26 ` [PATCH 2/4] x86: kvm: mmu: make spte mmio mask more explicit Peter Feiner
2017-07-01  0:26 ` [PATCH 3/4] kvm: x86: mmu: allow A/D bits to be disabled in an mmu Peter Feiner
2017-07-03  9:22   ` Paolo Bonzini
2017-07-01  0:26 ` [PATCH 4/4] x86: kvm: mmu: use ept a/d in vmcs02 iff used in vmcs12 Peter Feiner
2017-07-01  5:29   ` Paolo Bonzini [this message]
2017-07-01  7:29     ` Peter Feiner
2017-07-01  7:59       ` Paolo Bonzini

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