[Patch] Implement emulation of "pop reg" instruction

["Kamble, Nitin A" <nitin.a.kamble-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>]

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Hi Avi,
    Patch implementing the "pop reg", opcodes 0x58-0x5f attached. It has
passed the checkpatch.pl test. And you should not see any CRLF
characters in the attachment.

Please Comment/Apply.
  
Thanks & Regards,
Nitin 
Open Source Technology Center, Intel Corporation.
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commit 2f0a1268eb02f2b69ac75519083baa2419007dff
Author: Nitin A Kamble <nitin.a.kamble@intel.com>
Date:   Mon Jun 18 19:39:59 2007 -0700

    Implementing emulation of "pop reg" instruction (opcode 0x58- 0x5f).
    
    
    Signed-off-by: Nitin A Kamble <nitin.a.kamble@intel.com>

diff --git a/drivers/kvm/x86_emulate.c b/drivers/kvm/x86_emulate.c
index 59511c6..c09ae5b 100644
--- a/drivers/kvm/x86_emulate.c
+++ b/drivers/kvm/x86_emulate.c
@@ -98,8 +98,11 @@ static u8 opcode_table[256] = {
 	0, 0, 0, 0,
 	/* 0x40 - 0x4F */
 	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-	/* 0x50 - 0x5F */
-	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	/* 0x50 - 0x57 */
+	0, 0, 0, 0, 0, 0, 0, 0,
+	/* 0x58 - 0x5F */
+	ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
+	ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
 	/* 0x60 - 0x6F */
 	0, 0, 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
 	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -1153,6 +1156,16 @@ special_insn:
 	case 0xf4:              /* hlt */
 		ctxt->vcpu->halt_request = 1;
 		goto done;
+	case 0x58 ... 0x5f: /* pop reg */
+		dst.ptr = (unsigned long *)&_regs[b & 0x7];
+
+		if ((rc = ops->read_std(register_address(ctxt->ss_base,
+			_regs[VCPU_REGS_RSP]), dst.ptr, op_bytes, ctxt)) != 0)
+			goto done;
+
+		register_address_increment(_regs[VCPU_REGS_RSP], dst.bytes);
+		dst.orig_val = dst.val; /* Disable writeback. */
+		break;
 	}
 	goto writeback;
 

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