From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rusty Russell Subject: [PATCH 10/10] Use standard CR8 flags, and fix TPR definition Date: Tue, 17 Jul 2007 23:37:17 +1000 Message-ID: <1184679437.10380.31.camel@localhost.localdomain> References: <1184677946.10380.4.camel@localhost.localdomain> <1184678060.10380.7.camel@localhost.localdomain> <1184678129.10380.10.camel@localhost.localdomain> <1184678171.10380.12.camel@localhost.localdomain> <1184678216.10380.14.camel@localhost.localdomain> <1184678275.10380.16.camel@localhost.localdomain> <1184678348.10380.19.camel@localhost.localdomain> <1184679175.10380.25.camel@localhost.localdomain> <1184679256.10380.27.camel@localhost.localdomain> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Cc: kvm-devel , lkml - Kernel Mailing List , "H. Peter Anvin" To: Avi Kivity Return-path: In-Reply-To: <1184679256.10380.27.camel-bi+AKbBUZKY6gyzm1THtWbp2dZbC/Bob@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: kvm-devel-bounces-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org Errors-To: kvm-devel-bounces-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org List-Id: kvm.vger.kernel.org Intel manual (and KVM definition) say it's TPR is 4 bits wide. Also fix CR8_RESEVED_BITS typo. Signed-off-by: Rusty Russell diff -r 6ef0b4c0d6f7 drivers/kvm/kvm_main.c --- a/drivers/kvm/kvm_main.c Tue Jul 17 18:07:48 2007 +1000 +++ b/drivers/kvm/kvm_main.c Tue Jul 17 18:20:22 2007 +1000 @@ -92,7 +92,7 @@ static struct dentry *debugfs_dir; | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \ | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE)) -#define CR8_RESEVED_BITS (~0x0fULL) +#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR) #define EFER_RESERVED_BITS 0xfffffffffffff2fe #ifdef CONFIG_X86_64 @@ -633,7 +633,7 @@ EXPORT_SYMBOL_GPL(set_cr3); void set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) { - if ( cr8 & CR8_RESEVED_BITS) { + if (cr8 & CR8_RESERVED_BITS) { printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8); inject_gp(vcpu); return; diff -r 6ef0b4c0d6f7 include/asm-i386/processor-flags.h --- a/include/asm-i386/processor-flags.h Tue Jul 17 18:07:48 2007 +1000 +++ b/include/asm-i386/processor-flags.h Tue Jul 17 18:12:54 2007 +1000 @@ -63,7 +63,7 @@ /* * x86-64 Task Priority Register, CR8 */ -#define X86_CR8_TPR 0x00000007 /* task priority register */ +#define X86_CR8_TPR 0x0000000F /* task priority register */ /* * AMD and Transmeta use MSRs for configuration; see ------------------------------------------------------------------------- This SF.net email is sponsored by DB2 Express Download DB2 Express C - the FREE version of DB2 express and take control of your XML. No limits. Just data. Click to get it now. http://sourceforge.net/powerbar/db2/