From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rusty Russell Subject: Re: [PATCH] lmsw sets lower 16 bits of cr0, not just lower 4 Date: Thu, 02 Aug 2007 09:32:23 +1000 Message-ID: <1186011143.6131.130.camel@localhost.localdomain> References: <1185928308.6131.116.camel@localhost.localdomain> <46B0D4A8.7040001@qumranet.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Cc: kvm-devel To: Avi Kivity Return-path: In-Reply-To: <46B0D4A8.7040001-atKUWr5tajBWk0Htik3J/w@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: kvm-devel-bounces-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org Errors-To: kvm-devel-bounces-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org List-Id: kvm.vger.kernel.org On Wed, 2007-08-01 at 21:44 +0300, Avi Kivity wrote: > Rusty Russell wrote: > > According to my Intel manual, although lmsw only causes an exit when > > trying to set the bottom 4 bits, it is supposed to set the bottom 16 > > bits of cr0. > > > > > > Well, _my_ Intel manual (2A) says: > > > Loads the source operand into the machine status word, bits 0 through > > 15 of register CR0. The > > source operand can be a 16-bit general-purpose register or a memory > > location. Only the low- > > order 4 bits of the source operand (which contains the PE, MP, EM, and > > TS flags) are loaded Damn, I should have kept reading. Sorry for the noise! Rusty. ------------------------------------------------------------------------- This SF.net email is sponsored by: Splunk Inc. Still grepping through log files to find problems? Stop. Now Search log events and configuration files using AJAX and a browser. Download your FREE copy of Splunk now >> http://get.splunk.com/