[PATCH][UPDATE] kvm-userspace: sync icache for more architectures

[Christian Ehrhardt <ehrhardt-23VcF4HTsmIX0ybBhKVfKdBPR1lH4CV8@public.gmane.org>]

Subject: [PATCH][UPDATE] kvm-userspace: sync icache for more architectures
From: Christian Ehrhardt <ehrhardt-23VcF4HTsmIX0ybBhKVfKdBPR1lH4CV8@public.gmane.org>

A ia64 patch introduced kvm_sync_icache within a ifdef __ia64__, but the 
concept of split caches is not bound to ia64 and we would like to implement
it for ppc too.
The call to kvm_synch_icache is replaced by the flush_icache_range function
that is already available in qemu for ia64 and ppc (noop for x86). The call
now depends on USE_KVM.
This patch supersedes my old "[PATCH] kvm-userspace: kvm_sync_icache for more 
architectures" from this morning. 
The current ppc code around is not yet ready (it compiles & works for x86),
could someone please test&verify this patch for ia64?

Signed-off-by: Christian Ehrhardt <ehrhardt-23VcF4HTsmIX0ybBhKVfKdBPR1lH4CV8@public.gmane.org>

diff --git a/qemu/exec.c b/qemu/exec.c
index cf14fdd..d2a8f5b 100644
--- a/qemu/exec.c
+++ b/qemu/exec.c
@@ -35,6 +35,7 @@
 #include "cpu.h"
 #include "exec-all.h"
 #ifdef USE_KVM
+#include "dyngen.h"
 #include "qemu-kvm.h"
 #endif
 #if defined(CONFIG_USER_ONLY)
@@ -2600,8 +2601,8 @@ void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
                     phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |=
                         (0xff & ~CODE_DIRTY_FLAG);
                 }
-#ifdef __ia64__
-		kvm_sync_icache((unsigned long)ptr, l);
+#ifdef USE_KVM
+		flush_icache_range((unsigned long)ptr, ((unsigned long)ptr)+l);
 #endif
             }
         } else {
diff --git a/qemu/hw/ipf.c b/qemu/hw/ipf.c
index 957e831..8686c1e 100644
--- a/qemu/hw/ipf.c
+++ b/qemu/hw/ipf.c
@@ -105,17 +105,6 @@ static void pc_init_ne2k_isa(NICInfo *nd, qemu_irq *pic)
 #ifdef USE_KVM
 extern kvm_context_t kvm_context;
 extern int kvm_allowed;
-
-void kvm_sync_icache(unsigned long address, int len)
-{
-	int l;
-
-	for(l = 0; l < (len + 32); l += 32)
-		__ia64_fc(address + l);
-
-	ia64_sync_i();
-	ia64_srlz_i();
-}
 #endif
 
 static void main_cpu_reset(void *opaque)
diff --git a/qemu/target-ia64/cpu.h b/qemu/target-ia64/cpu.h
index 7349e94..be409c7 100644
--- a/qemu/target-ia64/cpu.h
+++ b/qemu/target-ia64/cpu.h
@@ -73,9 +73,4 @@ CPUState *cpu_ia64_init(void);
 
 #include "cpu-all.h"
 
-/* IA64 has seperate I/D cache, with coherence maintained by DMA controller.
- * So to emulate right behavior that guest OS is assumed, we need to flush
- * I/D cache here.
- */
-void kvm_sync_icache(unsigned long address, int len);
 #endif

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