From mboxrd@z Thu Jan 1 00:00:00 1970 From: Laurent Vivier Subject: Re: [PATCH 7/7] qemu: delayed MMIO support (e1000) Date: Mon, 26 May 2008 16:27:58 +0200 Message-ID: <1211812078.3908.31.camel@frecb07144> References: <12115326462681-git-send-email-Laurent.Vivier@bull.net> <12115326463363-git-send-email-Laurent.Vivier@bull.net> <12115326464029-git-send-email-Laurent.Vivier@bull.net> <1211532646540-git-send-email-Laurent.Vivier@bull.net> <12115326461479-git-send-email-Laurent.Vivier@bull.net> <12115326462379-git-send-email-Laurent.Vivier@bull.net> <12115326462508-git-send-email-Laurent.Vivier@bull.net> <12115326461790-git-send-email-Laurent.Vivier@bull.net> <483AC3AC.30801@qumranet.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: QUOTED-PRINTABLE Cc: kvm@vger.kernel.org To: Avi Kivity Return-path: Received: from ecfrec.frec.bull.fr ([129.183.4.8]:34264 "EHLO ecfrec.frec.bull.fr" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755199AbYEZO1g (ORCPT ); Mon, 26 May 2008 10:27:36 -0400 In-Reply-To: <483AC3AC.30801@qumranet.com> Sender: kvm-owner@vger.kernel.org List-ID: Le lundi 26 mai 2008 =C3=A0 17:05 +0300, Avi Kivity a =C3=A9crit : > Laurent Vivier wrote: > > This patch defines delayed MMIO zones for e1000 ethernet card. > > > > Signed-off-by: Laurent Vivier > > --- > > qemu/hw/e1000.c | 17 +++++++++++++++++ > > 1 files changed, 17 insertions(+), 0 deletions(-) > > > > diff --git a/qemu/hw/e1000.c b/qemu/hw/e1000.c > > index 01f8983..97f46f6 100644 > > --- a/qemu/hw/e1000.c > > +++ b/qemu/hw/e1000.c > > @@ -26,6 +26,7 @@ > > #include "hw.h" > > #include "pci.h" > > #include "net.h" > > +#include "qemu-kvm.h" > > =20 > > #include "e1000_hw.h" > > =20 > > @@ -938,6 +939,22 @@ e1000_mmio_map(PCIDevice *pci_dev, int region_= num, > > =20 > > d->mmio_base =3D addr; > > cpu_register_physical_memory(addr, PNPMMIO_SIZE, d->mmio_index= ); > > + > > + if (kvm_enabled()) { > > + /* delayed zones are: > > + * 0x00000 -> 0x000C0 exclude: E1000_ICR,4 > > + * 0x000C4 -> 0x00400 exclude: E1000_TCTL,4 > > + * 0x00404 -> 0x03818 exclude: E1000_TDT,4 > > + * 0x0381C -> 0x20000 PNPMMIO_SIZE > > + */ > > + qemu_kvm_register_delayed_mmio(addr, E1000_ICR); > > + qemu_kvm_register_delayed_mmio(addr + E1000_ICR + 4, > > + E1000_TCTL - (E1000_ICR + 4= )); > > + qemu_kvm_register_delayed_mmio(addr + E1000_TCTL + 4, > > + E1000_TDT - (E1000_TCTL + 4= )); > > + qemu_kvm_register_delayed_mmio(addr + E1000_TDT + 4, > > + PNPMMIO_SIZE - (E1000_TDT += 4)); > > + } > > } > > =20 >=20 > What about the calls to set_ics()? They can cause interrupts to be=20 > deasserted AFAICS. So IMC (and maybe a few other registers) need to = be=20 > excluded as well. Well, I don't know how I missed them... > Instead of hardcoding this, how about a >=20 > uint32_t delayed_mmi_excluded_regs[] =3D { > E1000_ICR, E1000_TCTL, ... > }; >=20 > The code can sort them and generate the ranges automatically. >=20 > (alternatively, a boolmap: >=20 > bool delayed_mmi_excluded_regs[] =3D { > [E1000_ICR]: true, ... > }; > ) I'll try... Regards, Laurent --=20 ------------- Laurent.Vivier@bull.net --------------- "The best way to predict the future is to invent it." - Alan Kay