From mboxrd@z Thu Jan 1 00:00:00 1970 From: john stultz Subject: Re: [patch 0/7] force the TSC unreliable by reporting C2 state Date: Wed, 18 Jun 2008 15:57:16 -0700 Message-ID: <1213829836.6433.10.camel@localhost.localdomain> References: <20080618164205.108219607@localhost.localdomain> <48596B85.7090008@codemonkey.ws> <20080618204042.GA15981@dmt.cnet> <485977EF.3090002@codemonkey.ws> <20080618212106.GA19602@dmt.cnet> <48598150.604@codemonkey.ws> <20080618224118.GA23236@dmt.cnet> Mime-Version: 1.0 Content-Type: text/plain Content-Transfer-Encoding: 7bit Cc: Anthony Liguori , Avi Kivity , kvm@vger.kernel.org, "Yang, Sheng" To: Marcelo Tosatti Return-path: Received: from e3.ny.us.ibm.com ([32.97.182.143]:47078 "EHLO e3.ny.us.ibm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752559AbYFRW5c (ORCPT ); Wed, 18 Jun 2008 18:57:32 -0400 Received: from d01relay04.pok.ibm.com (d01relay04.pok.ibm.com [9.56.227.236]) by e3.ny.us.ibm.com (8.13.8/8.13.8) with ESMTP id m5IMvRO1018549 for ; Wed, 18 Jun 2008 18:57:27 -0400 Received: from d01av04.pok.ibm.com (d01av04.pok.ibm.com [9.56.224.64]) by d01relay04.pok.ibm.com (8.13.8/8.13.8/NCO v9.0) with ESMTP id m5IMvJm7238922 for ; Wed, 18 Jun 2008 18:57:19 -0400 Received: from d01av04.pok.ibm.com (loopback [127.0.0.1]) by d01av04.pok.ibm.com (8.12.11.20060308/8.13.3) with ESMTP id m5IMvJnE002038 for ; Wed, 18 Jun 2008 18:57:19 -0400 In-Reply-To: <20080618224118.GA23236@dmt.cnet> Sender: kvm-owner@vger.kernel.org List-ID: On Wed, 2008-06-18 at 19:41 -0300, Marcelo Tosatti wrote: > On Wed, Jun 18, 2008 at 04:42:40PM -0500, Anthony Liguori wrote: > > Marcelo Tosatti wrote: > >> On Wed, Jun 18, 2008 at 04:02:39PM -0500, Anthony Liguori wrote: > >> > >>>>> Have we yet determined why the TSC is so unstable in the first > >>>>> place? In theory, it should be relatively stable on single-node > >>>>> Intel and Barcelona chips. > >>>>> > >>>> If the host enters C2/C3, or changes CPU frequency, it becomes > >>>> unreliable as a clocksource and there's no guarantee the guest will > >>>> detect that. > >>>> > >>> On Intel, the TSC should be fixed-frequency for basically all > >>> shipping processors supporting VT. Starting with 10h (Barcelona), I > >>> believe AMD also has a fixed frequency TSC. > >>> > >> > >> But still stops ticking in C2/C3 state, I suppose? > >> > > > > I don't know for sure but the TSC is not tied to the CPU clock so I > > would be surprised if it did. I think that that would defeat the > > utility of a fixed-frequency TSC. > > Well, Linux assumes that TSC stops ticking on C2/C3. > > Section 18.10 of Intel says: > > "The specific processor configuration determines the behavior. Constant > TSC behavior ensures that the duration of each clock tick is uniform and > supports the use of the TSC as a wall clock timer even if the processor > core changes frequency. This is the architectural behavior moving > forward." > > However it does not mention C2/C3. > > Could someone confirm either way? My understanding: On most systems, the TSC halts in C3. C2 may also halt the TSC, but that seems to depend on the BIOS. thanks -john