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From: Alexander Graf <agraf@suse.de>
To: kvm@vger.kernel.org
Cc: joro@8bytes.org, anthony@codemonkey.ws, avi@redhat.com
Subject: [PATCH 02/12] Move EFER and MSR constants to generic x86 code v6
Date: Fri, 21 Nov 2008 16:14:32 +0100	[thread overview]
Message-ID: <1227280482-25361-3-git-send-email-agraf@suse.de> (raw)
In-Reply-To: <1227280482-25361-2-git-send-email-agraf@suse.de>

MSR_EFER_SVME_MASK, MSR_VM_CR and MSR_VM_HSAVE_PA are set in KVM
specific headers. Linux does have nice header files to collect
EFER bits and MSR IDs, so IMHO we should put them there.

While at it, I also changed the naming scheme to match that
of the other defines.

(introduced in v6)

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 arch/x86/include/asm/kvm_host.h  |    1 +
 arch/x86/include/asm/msr-index.h |    7 +++++++
 arch/x86/kvm/svm.c               |    8 ++++----
 arch/x86/kvm/svm.h               |    4 ----
 4 files changed, 12 insertions(+), 8 deletions(-)

diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
index 99e3cc1..d96be80 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -22,6 +22,7 @@
 #include <asm/pvclock-abi.h>
 #include <asm/desc.h>
 #include <asm/mtrr.h>
+#include <asm/msr-index.h>
 
 #define KVM_MAX_VCPUS 16
 #define KVM_MEMORY_SLOTS 32
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index e38859d..e7625b1 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -18,11 +18,13 @@
 #define _EFER_LME		8  /* Long mode enable */
 #define _EFER_LMA		10 /* Long mode active (read-only) */
 #define _EFER_NX		11 /* No execute enable */
+#define _EFER_SVME		12 /* Enable virtualization */
 
 #define EFER_SCE		(1<<_EFER_SCE)
 #define EFER_LME		(1<<_EFER_LME)
 #define EFER_LMA		(1<<_EFER_LMA)
 #define EFER_NX			(1<<_EFER_NX)
+#define EFER_SVME		(1<<_EFER_SVME)
 
 /* Intel MSRs. Some also available on other CPUs */
 #define MSR_IA32_PERFCTR0		0x000000c1
@@ -329,4 +331,9 @@
 #define MSR_IA32_VMX_PROCBASED_CTLS2    0x0000048b
 #define MSR_IA32_VMX_EPT_VPID_CAP       0x0000048c
 
+/* AMD-V MSRs */
+
+#define MSR_VM_CR                       0xc0010114
+#define MSR_VM_HSAVE_PA                 0xc0010117
+
 #endif /* _ASM_X86_MSR_INDEX_H */
diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index d80b3fa..d7bf0a6 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -196,7 +196,7 @@ static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 	if (!npt_enabled && !(efer & EFER_LMA))
 		efer &= ~EFER_LME;
 
-	to_svm(vcpu)->vmcb->save.efer = efer | MSR_EFER_SVME_MASK;
+	to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 	vcpu->arch.shadow_efer = efer;
 }
 
@@ -272,7 +272,7 @@ static void svm_hardware_disable(void *garbage)
 
 	wrmsrl(MSR_VM_HSAVE_PA, 0);
 	rdmsrl(MSR_EFER, efer);
-	wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK);
+	wrmsrl(MSR_EFER, efer & ~EFER_SVME);
 }
 
 static void svm_hardware_enable(void *garbage)
@@ -305,7 +305,7 @@ static void svm_hardware_enable(void *garbage)
 	svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 
 	rdmsrl(MSR_EFER, efer);
-	wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK);
+	wrmsrl(MSR_EFER, efer | EFER_SVME);
 
 	wrmsrl(MSR_VM_HSAVE_PA,
 	       page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
@@ -572,7 +572,7 @@ static void init_vmcb(struct vcpu_svm *svm)
 	init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 	init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 
-	save->efer = MSR_EFER_SVME_MASK;
+	save->efer = EFER_SVME;
 	save->dr6 = 0xffff0ff0;
 	save->dr7 = 0x400;
 	save->rflags = 2;
diff --git a/arch/x86/kvm/svm.h b/arch/x86/kvm/svm.h
index 1b8afa7..82ada75 100644
--- a/arch/x86/kvm/svm.h
+++ b/arch/x86/kvm/svm.h
@@ -174,10 +174,6 @@ struct __attribute__ ((__packed__)) vmcb {
 #define SVM_CPUID_FEATURE_SHIFT 2
 #define SVM_CPUID_FUNC 0x8000000a
 
-#define MSR_EFER_SVME_MASK (1ULL << 12)
-#define MSR_VM_CR       0xc0010114
-#define MSR_VM_HSAVE_PA 0xc0010117ULL
-
 #define SVM_VM_CR_SVM_DISABLE 4
 
 #define SVM_SELECTOR_S_SHIFT 4
-- 
1.5.6


  reply	other threads:[~2008-11-21 15:14 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2008-11-21 15:14 [PATCH 00/12] Add support for nested SVM (kernel) v6 Alexander Graf
2008-11-21 15:14 ` [PATCH 01/12] Clean up VINTR setting v6 Alexander Graf
2008-11-21 15:14   ` Alexander Graf [this message]
2008-11-21 15:14     ` [PATCH 03/12] Add helper functions for nested SVM v6 Alexander Graf
2008-11-21 15:14       ` [PATCH 04/12] Implement GIF, clgi and stgi v6 Alexander Graf
2008-11-21 15:14         ` [PATCH 05/12] Implement hsave v6 Alexander Graf
2008-11-21 15:14           ` [PATCH 06/12] Add VMLOAD and VMSAVE handlers v6 Alexander Graf
2008-11-21 15:14             ` [PATCH 07/12] Add VMRUN handler v6 Alexander Graf
2008-11-21 15:14               ` [PATCH 08/12] Add VMEXIT handler and intercepts v6 Alexander Graf
2008-11-21 15:14                 ` [PATCH 09/12] Allow read access to MSR_VM_VR v6 Alexander Graf
2008-11-21 15:14                   ` [PATCH 10/12] Allow setting the SVME bit v6 Alexander Graf
2008-11-21 15:14                     ` [PATCH 11/12] Only allow setting of EFER_SVME when CPUID SVM is set v6 Alexander Graf
2008-11-21 15:14                       ` [PATCH 12/12] Accelerate nested SVM by emulating parts of GIF=0 v6 Alexander Graf
2008-11-21 16:53                         ` Avi Kivity
2008-11-21 16:58                           ` Alexander Graf
2008-11-21 17:07                             ` Avi Kivity
2008-11-21 17:14                               ` Alexander Graf
2008-11-21 17:18                                 ` Avi Kivity
2008-11-21 17:35                                   ` Alexander Graf
2008-11-21 15:23               ` [PATCH 07/12] Add VMRUN handler v6 Muli Ben-Yehuda
2008-11-21 15:26                 ` Alexander Graf
2008-11-21 15:35                   ` Alexander Graf
2008-11-23  8:06                     ` Muli Ben-Yehuda
2008-11-23 13:48                       ` Alexander Graf
2008-11-23 15:09                         ` Muli Ben-Yehuda

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