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From: Andre Przywara <andre.przywara@amd.com>
To: Avi Kivity <avi@redhat.com>
Cc: Amit Shah <amit.shah@redhat.com>,
	kvm@vger.kernel.org, Andre Przywara <andre.przywara@amd.com>
Subject: [PATCH] [resend] set accessed bit for VMCB segment selectors
Date: Fri, 20 Feb 2009 15:31:45 +0100	[thread overview]
Message-ID: <12351403054013-git-send-email-andre.przywara@amd.com> (raw)

Avi, could you apply this patch to kvm.git and linux-2.6.29-rcx? It
fixes cross vendor migration with multithreaded guest applications.
Also the two cross-vendor migration patches (in this very place) from Amit from
October are not in upstream Linux, could you push (or pull-request) them?
Commit-IDs: 397248be81d79a3e03871b05d136e742a737b640
dc2a503e2f2fbab2dca788d49bb7057604db11b4


Thanks,
Andre.

-----------------
In the segment descriptor _cache_ the accessed bit is always set
(although it can be cleared in the descriptor itself). Since Intel
checks for this condition on a VMENTRY, set this bit in the AMD path
to enable cross vendor migration.

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
---
 arch/x86/kvm/svm.c |   23 +++++++++++++++++++++--
 1 files changed, 21 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index 22e88a4..dc5d88f 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -796,20 +796,39 @@ static void svm_get_segment(struct kvm_vcpu *vcpu,
 	var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
 	var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
 
+	switch (seg) {
 	/*
 	 * SVM always stores 0 for the 'G' bit in the CS selector in
 	 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
 	 * Intel's VMENTRY has a check on the 'G' bit.
 	 */
-	if (seg == VCPU_SREG_CS)
+	case VCPU_SREG_CS:
 		var->g = s->limit > 0xfffff;
+		break;
 
 	/*
 	 * Work around a bug where the busy flag in the tr selector
 	 * isn't exposed
 	 */
-	if (seg == VCPU_SREG_TR)
+	case VCPU_SREG_TR:
 		var->type |= 0x2;
+		break;
+
+	/*
+	* The accessed bit must always be set in the segment
+	* descriptor cache, although it can be cleared in the
+	* descriptor, the cached bit always remains at 1. Since
+	* Intel has a check on this, set it here to support
+	* cross-vendor migration.
+	*/
+	case VCPU_SREG_DS:
+	case VCPU_SREG_ES:
+	case VCPU_SREG_FS:
+	case VCPU_SREG_GS:
+		if (!var->unusable)
+			var->type |= 0x1;
+		break;
+	}
 
 	var->unusable = !var->present;
 }
-- 
1.5.2.2



             reply	other threads:[~2009-02-20 14:47 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2009-02-20 14:31 Andre Przywara [this message]
2009-02-23 10:28 ` [PATCH] [resend] set accessed bit for VMCB segment selectors Avi Kivity

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