Re: [PATCH -v2] Add MCE support to KVM

[Huang Ying <ying.huang@intel.com>]

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On Mon, 2009-04-20 at 11:57 +0800, Kyle Moffett wrote:
> On Sun, Apr 19, 2009 at 9:19 PM, Huang Ying <ying.huang@intel.com> wrote:
> > On Sat, 2009-04-18 at 23:54 +0800, Anthony Liguori wrote:
> >> Huang Ying wrote:
> >> > The related MSRs are emulated. MCE capability is exported via
> >> > extension KVM_CAP_MCE and ioctl KVM_X86_GET_MCE_CAP_SUPPORTED. A new
> >> > vcpu ioctl command KVM_X86_SETUP_MCE is used to setup MCE emulation
> >> > such as the mcg_cap. MCE is injected via vcpu ioctl command
> >> > KVM_X86_SET_MCE. Extended machine-check state (MCG_EXT_P) and CMCI are
> >> > not simulated.
> >> >
> >>
> >> Maybe I'm missing something, but couldn't this be implemented entirely
> >> within userspace?  There's nothing VT/SVM specific about this.  If the
> >> issue is setting these MSRs from userspace via KVM_SET_MSRS isn't
> >> enough, perhaps we should add userspace MSR handling.
> >>
> >> Also, if you implement the MSR logic in userspace, it's pretty simple to
> >> make it work in the non-TCG case which will be a requirement for
> >> upstream merging.
> >
> > There is more logic than just KVM_SET_MSRS, such as BANK reporting
> > disabling, overwriting rules, triple fault for UC MCE during MCIP.
> > Although these logic can be implemented in user space, I think put them
> > in kernel space is easy to be understood. And the code is pretty short.
> 
> IMO the main reason to put this in kernel-space would be to make it
> possible to automatically forward some MCE errors generated by the
> real hardware (RAM ECC errors for example) down into the VM.  Right
> now I suppose you could do that with the patches to forward RAM-based
> hard MCEs to userspace using SIGSEGV and handling the SIGSEGV in
> userspace, but that seems more fragile to me.

Yes. Puting this in kernel-space would make it more reliable to forward
the MCE to KVM guest.

Best Regards,
Huang Ying

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