[PATCH 0/3] Cache PDPTRs under ept/npt

[Avi Kivity <avi@redhat.com>]

Currently the EPT code re-loads the PDPTRs after every exit, even though
they usually are not needed.  Moreover, the PDPTRs are reloaded from memory,
even though they are supposed to be kept on processor registers independent
from memory.  The NPT case is similar.

This patchset makes the PDPTRs cacheable registers (like RSP and RIP on vmx)
so they are only stored in the VMCS if they are dirtied and copied from the
VMCS to memory on demand.  As SVM doesn't virtualize the PDPTRs, we simple
load them from memory on demand (instead of on every exit).

It reduces ept vmexit costs (inb on some pic port) from 3231 cycles to 2750
cycles, a 15% reduction.

Please review.

Avi Kivity (3):
  KVM: VMX: Avoid duplicate ept tlb flush when setting cr3
  KVM: VMX: Simplify pdptr and cr3 management
  KVM: Cache pdptrs

 arch/x86/include/asm/kvm_host.h |    4 +++
 arch/x86/kvm/kvm_cache_regs.h   |   10 +++++++++
 arch/x86/kvm/mmu.c              |    7 ++++-
 arch/x86/kvm/paging_tmpl.h      |    2 +-
 arch/x86/kvm/svm.c              |   24 ++++++++++++++++-----
 arch/x86/kvm/vmx.c              |   42 +++++++++++++++++++++++++++++---------
 arch/x86/kvm/x86.c              |    8 +++++++
 7 files changed, 78 insertions(+), 19 deletions(-)