From mboxrd@z Thu Jan 1 00:00:00 1970 From: Nitin A Kamble Subject: Re: [patch] VMX Unrestricted mode support Date: Wed, 03 Jun 2009 11:18:10 -0700 Message-ID: <1244053090.26481.25.camel@mukti.sc.intel.com> References: <1243552292.25456.23.camel@mukti.sc.intel.com> <4A224229.6090108@redhat.com> <1243879609.30052.1.camel@mukti.sc.intel.com> <1243881334.30052.2.camel@mukti.sc.intel.com> <4A24201A.5060409@redhat.com> <1244052535.26481.22.camel@mukti.sc.intel.com> Mime-Version: 1.0 Content-Type: text/plain Content-Transfer-Encoding: 7bit Cc: "kvm@vger.kernel.org" , jun.nakajima@intel.com To: Avi Kivity Return-path: Received: from mga09.intel.com ([134.134.136.24]:61990 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751988AbZFCSSS (ORCPT ); Wed, 3 Jun 2009 14:18:18 -0400 In-Reply-To: <1244052535.26481.22.camel@mukti.sc.intel.com> Sender: kvm-owner@vger.kernel.org List-ID: Avi, I also tested the qemu change is not affecting vm86 (no unrestricted guest) code path. Thanks & Regards, Nitin On Wed, 2009-06-03 at 11:08 -0700, Nitin A Kamble wrote: > Hi Avi, > I find that the qemu processor reset state is not per the IA32 > processor specifications. (Sections 8.1.1 of > http://www.intel.com/Assets/PDF/manual/253668.pdf) > > In qemu-kvm.git in file target-i386/helper.c in function cpu_reset the > segment registers are initialized as follows: > > cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, > DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | > DESC_R_MASK); > cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, > DESC_P_MASK | DESC_S_MASK | DESC_W_MASK); > cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, > DESC_P_MASK | DESC_S_MASK | DESC_W_MASK); > cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, > DESC_P_MASK | DESC_S_MASK | DESC_W_MASK); > cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, > DESC_P_MASK | DESC_S_MASK | DESC_W_MASK); > cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, > DESC_P_MASK | DESC_S_MASK | DESC_W_MASK); > > While the IA32 cpu reset state specification says that Segment Accessed > bit is also 1 at the time of cpu reset. so the above code should look > like this: > > cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, > DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | > DESC_R_MASK | DESC_A_MASK); > cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, > DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | DESC_A_MASK); > cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, > DESC_P_MASK | DESC_S_MASK | DESC_W_MASK| DESC_A_MASK); > cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, > DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |DESC_A_MASK); > cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, > DESC_P_MASK | DESC_S_MASK | DESC_W_MASK); > cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, > DESC_P_MASK | DESC_S_MASK | DESC_W_MASK); > > This discrepancy is adding the need of the following function in the > unrestricted guest patch. > > +static inline u32 get_segment_ar(int seg) > +{ > + if (!enable_unrestricted_guest) > + return 0xf3; > + > + switch (seg) { > + case VCPU_SREG_CS: > + return 0x9b; > + case VCPU_SREG_TR: > + return 0x8b; > + case VCPU_SREG_LDTR: > + return 0x82; > + default: > + return 0x93; > + } > +} > + > > For the unrestricted guest support either we can fix this discrepancy in > the qemu code, or have a functionality like get_segment_ar() in the kvm > vmx code. > what do you suggest ? > > Thanks & Regards, > Nitin > > > -- > To unsubscribe from this list: send the line "unsubscribe kvm" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html