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From: Andre Przywara <andre.przywara@amd.com>
To: avi@redhat.com
Cc: kvm@vger.kernel.org, Andre Przywara <andre.przywara@amd.com>
Subject: [PATCH 2/4] ignore reads from AMDs C1E enabled MSR
Date: Wed, 24 Jun 2009 12:44:34 +0200	[thread overview]
Message-ID: <1245840276-12702-2-git-send-email-andre.przywara@amd.com> (raw)
In-Reply-To: <1245840276-12702-1-git-send-email-andre.przywara@amd.com>

If the Linux kernel detects an C1E capable AMD processor (K8 RevF and
higher), it will access a certain MSR on every attempt to go to halt.
Explicitly handle this read and return 0 to let KVM run a Linux guest
with the native AMD host CPU propagated to the guest.

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
---
 arch/x86/kvm/x86.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index c5a0d37..a148f4c 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -1001,6 +1001,7 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
 	case MSR_P6_EVNTSEL0:
 	case MSR_P6_EVNTSEL1:
 	case MSR_K7_EVNTSEL0:
+	case MSR_K8_INT_PENDING_MSG:
 		data = 0;
 		break;
 	case MSR_MTRRcap:
-- 
1.6.1.3



  reply	other threads:[~2009-06-24 10:41 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2009-06-24 10:44 [PATCH 1/4] ignore AMDs HWCR register access to set the FFDIS bit Andre Przywara
2009-06-24 10:44 ` Andre Przywara [this message]
2009-06-24 10:44   ` [PATCH 3/4] ignore PCI ECS I/O enablement Andre Przywara
2009-06-24 10:44     ` [PATCH 4/4] dont trim the guest's hypervisor CPUID bit in KVM if the guest requests it Andre Przywara
2009-06-24 11:28       ` Avi Kivity
2009-06-24 12:28         ` Andre Przywara
2009-06-24 13:28           ` Andre Przywara
2009-06-24 11:31     ` [PATCH 3/4] ignore PCI ECS I/O enablement Avi Kivity
2009-06-24 13:37       ` Andre Przywara
2009-07-01  9:50         ` Avi Kivity
2009-06-24 11:37 ` [PATCH 1/4] ignore AMDs HWCR register access to set the FFDIS bit Avi Kivity

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