From: Andre Przywara <andre.przywara@amd.com>
To: avi@redhat.com
Cc: kvm@vger.kernel.org, Andre Przywara <andre.przywara@amd.com>
Subject: [PATCH 3/4] ignore PCI ECS I/O enablement
Date: Wed, 24 Jun 2009 12:44:35 +0200 [thread overview]
Message-ID: <1245840276-12702-3-git-send-email-andre.przywara@amd.com> (raw)
In-Reply-To: <1245840276-12702-2-git-send-email-andre.przywara@amd.com>
Linux guests will try to enable access to the extended PCI config space
via the I/O ports 0xCF8/0xCFC on AMD Fam10h CPU. Since we (currently?)
don't use ECS, simply ignore this write attempt.
Signed-off-by: Andre Przywara <andre.przywara@amd.com>
---
arch/x86/kvm/x86.c | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index a148f4c..e6e61ee 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -804,6 +804,8 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
return 1;
}
break;
+ case MSR_AMD64_NB_CFG:
+ break;
case MSR_IA32_DEBUGCTLMSR:
if (!data) {
/* We support the non-activated case already */
--
1.6.1.3
next prev parent reply other threads:[~2009-06-24 10:41 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-06-24 10:44 [PATCH 1/4] ignore AMDs HWCR register access to set the FFDIS bit Andre Przywara
2009-06-24 10:44 ` [PATCH 2/4] ignore reads from AMDs C1E enabled MSR Andre Przywara
2009-06-24 10:44 ` Andre Przywara [this message]
2009-06-24 10:44 ` [PATCH 4/4] dont trim the guest's hypervisor CPUID bit in KVM if the guest requests it Andre Przywara
2009-06-24 11:28 ` Avi Kivity
2009-06-24 12:28 ` Andre Przywara
2009-06-24 13:28 ` Andre Przywara
2009-06-24 11:31 ` [PATCH 3/4] ignore PCI ECS I/O enablement Avi Kivity
2009-06-24 13:37 ` Andre Przywara
2009-07-01 9:50 ` Avi Kivity
2009-06-24 11:37 ` [PATCH 1/4] ignore AMDs HWCR register access to set the FFDIS bit Avi Kivity
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