From mboxrd@z Thu Jan 1 00:00:00 1970 From: Benjamin Herrenschmidt Subject: Re: [PATCH 18/26] KVM: PPC: KVM PV guest stubs Date: Mon, 28 Jun 2010 08:04:59 +1000 Message-ID: <1277676299.4200.132.camel@pasglop> References: <1277508314-915-1-git-send-email-agraf@suse.de> <1277508314-915-19-git-send-email-agraf@suse.de> <4C270BB8.60404@redhat.com> <0E529B3E-541C-4E3B-81E7-AACCD96CBF2C@suse.de> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Cc: "kvm-ppc@vger.kernel.org" , linuxppc-dev , Avi Kivity , KVM list To: Alexander Graf Return-path: In-Reply-To: <0E529B3E-541C-4E3B-81E7-AACCD96CBF2C@suse.de> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linuxppc-dev-bounces+glppe-linuxppc-embedded-2=m.gmane.org@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+glppe-linuxppc-embedded-2=m.gmane.org@lists.ozlabs.org List-Id: kvm.vger.kernel.org On Sun, 2010-06-27 at 11:47 +0200, Alexander Graf wrote: > I did that at first. It breaks. During the patching we may take > interrupts (pahe faults for example) that contain just patched > instructions. And really, hell breaks loose if we don't flush it > immediately :). I was hoping at first a 32 bit replace would be > atomic > in cache, but the cpu tried to execute invalid instructions, so it > must have gotten some intermediate state. A 32-bit aligned store -is- atomic. The other threads/cpu will see either the old or the new instruction, nothing in between. Cheers, Ben.