From mboxrd@z Thu Jan 1 00:00:00 1970 From: Benjamin Herrenschmidt Subject: Re: [PATCH 27/27] KVM: PPC: Add Documentation about PV interface Date: Sun, 04 Jul 2010 08:42:36 +1000 Message-ID: <1278196956.4200.390.camel@pasglop> References: <1277980982-12433-1-git-send-email-agraf@suse.de> <1277980982-12433-28-git-send-email-agraf@suse.de> Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit Cc: Segher Boessenkool , linuxppc-dev , KVM list , kvm-ppc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Alexander Graf Return-path: In-Reply-To: Sender: kvm-ppc-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: kvm.vger.kernel.org On Fri, 2010-07-02 at 20:41 +0200, Alexander Graf wrote: > The u64s are 64-bit aligned, should they always be? > > That's obvious, isn't it? And the ABI only specifies u64s to be 32 bit > aligned, no? At least that's what ld and std specify. No, the PowerPC ABI specifies u64's to be 64-bit aligned, even for 32-bit binaries. Ben. > > > >> +The "ld" and "std" instructions are transormed to "lwz" and "stw" > instructions > >> +respectively on 32 bit systems with an added offset of 4 to > accomodate for big > >> +endianness. > > > > Will this add never overflow? Is there anything that checks for it? > > It basically means that to access dar, we either do > > ld rX, DAR(0) > > or > > lwz rX, DAR+4(0) > > > > > >> +mtmsrd rX, 0 b > >> +mtmsr b > > > > mtmsr rX > > Nod.