From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sheng Yang Subject: [PATCH 1/6] PCI: MSI: Move MSI-X entry definition to pci_regs.h Date: Mon, 15 Nov 2010 17:15:27 +0800 Message-ID: <1289812532-3227-2-git-send-email-sheng@linux.intel.com> References: <1289812532-3227-1-git-send-email-sheng@linux.intel.com> Cc: Marcelo Tosatti , "Michael S. Tsirkin" , kvm@vger.kernel.org, Sheng Yang , linux-pci@vger.kernel.org To: Avi Kivity Return-path: Received: from mga02.intel.com ([134.134.136.20]:9011 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753277Ab0KOJOl (ORCPT ); Mon, 15 Nov 2010 04:14:41 -0500 In-Reply-To: <1289812532-3227-1-git-send-email-sheng@linux.intel.com> Sender: kvm-owner@vger.kernel.org List-ID: Then it can be used by others. Reviewed-by: Hidetoshi Seto Reviewed-by: Matthew Wilcox Acked-by: Jesse Barnes Cc: linux-pci@vger.kernel.org Signed-off-by: Sheng Yang --- drivers/pci/msi.h | 6 ------ include/linux/pci_regs.h | 7 +++++++ 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/pci/msi.h b/drivers/pci/msi.h index feff3be..65c42f8 100644 --- a/drivers/pci/msi.h +++ b/drivers/pci/msi.h @@ -6,12 +6,6 @@ #ifndef MSI_H #define MSI_H -#define PCI_MSIX_ENTRY_SIZE 16 -#define PCI_MSIX_ENTRY_LOWER_ADDR 0 -#define PCI_MSIX_ENTRY_UPPER_ADDR 4 -#define PCI_MSIX_ENTRY_DATA 8 -#define PCI_MSIX_ENTRY_VECTOR_CTRL 12 - #define msi_control_reg(base) (base + PCI_MSI_FLAGS) #define msi_lower_address_reg(base) (base + PCI_MSI_ADDRESS_LO) #define msi_upper_address_reg(base) (base + PCI_MSI_ADDRESS_HI) diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h index af83076..b21d33e 100644 --- a/include/linux/pci_regs.h +++ b/include/linux/pci_regs.h @@ -309,6 +309,13 @@ #define PCI_MSIX_PBA 8 #define PCI_MSIX_FLAGS_BIRMASK (7 << 0) +/* MSI-X entry's format */ +#define PCI_MSIX_ENTRY_SIZE 16 +#define PCI_MSIX_ENTRY_LOWER_ADDR 0 +#define PCI_MSIX_ENTRY_UPPER_ADDR 4 +#define PCI_MSIX_ENTRY_DATA 8 +#define PCI_MSIX_ENTRY_VECTOR_CTRL 12 + /* CompactPCI Hotswap Register */ #define PCI_CHSWP_CSR 2 /* Control and Status Register */ -- 1.7.0.1