From mboxrd@z Thu Jan 1 00:00:00 1970 From: Pawel Moll Subject: Re: [PATCHv2 RFC] virtio-spec: flexible configuration layout Date: Fri, 11 Nov 2011 13:06:57 +0000 Message-ID: <1321016817.3259.389.camel@hornet.cambridge.arm.com> References: <20111101124223.GA14060@redhat.com> <8739e7uy87.fsf@rustcorp.com.au> <20111102233110.GA20289@redhat.com> <20111108214021.GA4538@redhat.com> <20111109195901.GA28155@redhat.com> <1320870287.3730.6.camel@lappy> <20111109205208.GA28599@redhat.com> <1320872248.3730.11.camel@lappy> <87aa83qoao.fsf@rustcorp.com.au> <20111111125907.GB23902@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: QUOTED-PRINTABLE Cc: Sasha Levin , Rusty Russell , lkml - Kernel Mailing List , Alexey Kardashevskiy , Amit Shah , Christian Borntraeger , Krishna Kumar , Wang Sheng-Hui , "virtualization@lists.linux-foundation.org" , "kvm@vger.kernel.org" , "avi@redhat.com" , "penberg@kernel.org" To: "Michael S. Tsirkin" Return-path: In-Reply-To: <20111111125907.GB23902@redhat.com> Sender: linux-kernel-owner@vger.kernel.org List-Id: kvm.vger.kernel.org > > Also, an unrelated questions: With PIO, requests were ordered, whic= h > > means that if we wrote to the queue selector and then read from a > > queue register we would read the correct queue info. > > Is the same thing assured to us with MMIO? >=20 > For real PCI, reads do not bypass writes in PCI. However this > is only true if both are MMIO or both PIO reads. > I don't think the ordering of MMIO versus PIO is guaranteed. >=20 > On KVM, the kernel doesn't do anything to guarantee ordering. > So you get the natural ordering of the CPU. >=20 > > If we write to a queue > > selector and immediately read from queue info would we be reading t= he > > right info, or is there the slight chance that it would get reorder= ed > > and we would be reading queue info first and writing to the selecto= r > > later? >=20 > The thing to realize is that write to queue selector with KVM is in t= he > end performed by host. And reading queue info means that host will be > reading the queue selector. So this is a write followed by read > from the same address. AFAIK no CPUs can reorder such accesses, > so you get the right info. (As far as I understand all the complexity ;-) Memory mapped using ioremap()-like functions should preserve access order. In case of ARM architecture such memory region is defined (at the page tables level) a= s a "device memory" (contrary to "normal memory") and the processor will not try to be clever about it. I know next-to-nothing about x86, but I suppose similar idea applies. Cheers! Pawe=C5=82