* [PATCH v6 0/3] x86, apicv: Add APIC virtualization support
@ 2012-12-12 4:56 Yang Zhang
2012-12-12 4:56 ` [PATCH v6 1/3] x86, apicv: add APICv register " Yang Zhang
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Yang Zhang @ 2012-12-12 4:56 UTC (permalink / raw)
To: kvm; +Cc: mtosatti, gleb, haitao.shan, Yang Zhang
From: Yang Zhang <yang.z.zhang@Intel.com>
APIC virtualization is a new feature which can eliminate most of VM exit
when vcpu handle a interrupt:
APIC register virtualization:
APIC read access doesn't cause APIC-access VM exits.
APIC write becomes trap-like.
Virtual interrupt delivery:
Virtual interrupt delivery avoids KVM to inject vAPIC interrupts
manually, which is fully taken care of by the hardware.
Please refer to Intel SDM volume 3, chapter 29 for more details.
Changes v5 to v6:
* minor adjustments according gleb's comments
* Rebased on top of KVM upstream.
Changes v4 to v5:
* Set eoi exit bitmap when an interrupt has notifier registered.
* Use request to track ioapic entry's modification.
* Rebased on top of KVM upstream.
Changes v3 to v4:
* use one option to control both register virtualization and virtual interrupt
delivery.
* Update eoi exit bitmap when programing ioapic or programing apic's id/dfr/ldr.
* Rebased on top of KVM upstream.
Changes v2 to v3:
* Drop Posted Interrupt patch from v3.
According Gleb's suggestion, we will use global vector for all VCPUs as notification
event vector. So we will rewrite the Posted Interrupt patch. And resend it later.
* Use TMR to set the eoi exiting bitmap. We only want to set eoi exiting bitmap for
those interrupt which is level trigger or has notifier in EOI write path. So TMR is
enough to distinguish the interrupt trigger mode.
* Simplify some code according Gleb's comments.
* rebased on top of KVM upstream.
Changes v1 to v2:
* Add Posted Interrupt support in this series patch.
* Since there is a notifer hook in vAPIC EOI for PIT interrupt. So always Set PIT
interrupt in eoi exit bitmap to force vmexit when EOI to interrupt.
* Rebased on top of KVM upstream
Yang Zhang (3):
x86, apicv: add APICv register virtualization support
x86, apicv: add virtual interrupt delivery support
x86, apicv: add virtual x2apic support
arch/ia64/kvm/lapic.h | 6 +
arch/x86/include/asm/kvm_host.h | 5 +
arch/x86/include/asm/vmx.h | 13 +++
arch/x86/kvm/irq.c | 60 +++++++++++--
arch/x86/kvm/lapic.c | 114 +++++++++++++++++++++--
arch/x86/kvm/lapic.h | 11 ++
arch/x86/kvm/svm.c | 25 +++++
arch/x86/kvm/vmx.c | 193 +++++++++++++++++++++++++++++++++++++--
arch/x86/kvm/x86.c | 11 ++-
include/linux/kvm_host.h | 2 +
virt/kvm/ioapic.c | 33 +++++++
virt/kvm/ioapic.h | 1 +
virt/kvm/irq_comm.c | 20 ++++
13 files changed, 467 insertions(+), 27 deletions(-)
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v6 1/3] x86, apicv: add APICv register virtualization support
2012-12-12 4:56 [PATCH v6 0/3] x86, apicv: Add APIC virtualization support Yang Zhang
@ 2012-12-12 4:56 ` Yang Zhang
2012-12-12 4:56 ` [PATCH v6 2/3] x86, apicv: add virtual interrupt delivery support Yang Zhang
2012-12-12 4:56 ` [PATCH v6 3/3] x86, apicv: add virtual x2apic support Yang Zhang
2 siblings, 0 replies; 7+ messages in thread
From: Yang Zhang @ 2012-12-12 4:56 UTC (permalink / raw)
To: kvm; +Cc: mtosatti, gleb, haitao.shan, Yang Zhang, Kevin Tian
- APIC read doesn't cause VM-Exit
- APIC write becomes trap-like
Signed-off-by: Kevin Tian <kevin.tian@intel.com>
Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>
---
arch/x86/include/asm/vmx.h | 2 ++
arch/x86/kvm/lapic.c | 15 +++++++++++++++
arch/x86/kvm/lapic.h | 2 ++
arch/x86/kvm/vmx.c | 33 ++++++++++++++++++++++++++++++++-
4 files changed, 51 insertions(+), 1 deletions(-)
diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h
index 36ec21c..21101b6 100644
--- a/arch/x86/include/asm/vmx.h
+++ b/arch/x86/include/asm/vmx.h
@@ -66,6 +66,7 @@
#define EXIT_REASON_EPT_MISCONFIG 49
#define EXIT_REASON_WBINVD 54
#define EXIT_REASON_XSETBV 55
+#define EXIT_REASON_APIC_WRITE 56
#define EXIT_REASON_INVPCID 58
#define VMX_EXIT_REASONS \
@@ -141,6 +142,7 @@
#define SECONDARY_EXEC_ENABLE_VPID 0x00000020
#define SECONDARY_EXEC_WBINVD_EXITING 0x00000040
#define SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080
+#define SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100
#define SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400
#define SECONDARY_EXEC_ENABLE_INVPCID 0x00001000
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index 9392f52..0664c13 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -1212,6 +1212,21 @@ void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
}
EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
+/* emulate APIC access in a trap manner */
+void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
+{
+ u32 val = 0;
+
+ /* hw has done the conditional check and inst decode */
+ offset &= 0xff0;
+
+ apic_reg_read(vcpu->arch.apic, offset, 4, &val);
+
+ /* TODO: optimize to just emulate side effect w/o one more write */
+ apic_reg_write(vcpu->arch.apic, offset, val);
+}
+EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
+
void kvm_free_lapic(struct kvm_vcpu *vcpu)
{
struct kvm_lapic *apic = vcpu->arch.apic;
diff --git a/arch/x86/kvm/lapic.h b/arch/x86/kvm/lapic.h
index e5ebf9f..9a8ee22 100644
--- a/arch/x86/kvm/lapic.h
+++ b/arch/x86/kvm/lapic.h
@@ -64,6 +64,8 @@ int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu);
u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu);
void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data);
+void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset);
+
void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr);
void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu);
void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu);
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index 2fd2046..4838e4f 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -83,6 +83,9 @@ module_param(vmm_exclusive, bool, S_IRUGO);
static bool __read_mostly fasteoi = 1;
module_param(fasteoi, bool, S_IRUGO);
+static bool __read_mostly enable_apicv_reg_vid = 1;
+module_param(enable_apicv_reg_vid, bool, S_IRUGO);
+
/*
* If nested=1, nested virtualization is supported, i.e., guests may use
* VMX and be a hypervisor for its own guests. If nested=0, guests may not
@@ -761,6 +764,12 @@ static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
}
+static inline bool cpu_has_vmx_apic_register_virt(void)
+{
+ return vmcs_config.cpu_based_2nd_exec_ctrl &
+ SECONDARY_EXEC_APIC_REGISTER_VIRT;
+}
+
static inline bool cpu_has_vmx_flexpriority(void)
{
return cpu_has_vmx_tpr_shadow() &&
@@ -2498,7 +2507,8 @@ static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
SECONDARY_EXEC_UNRESTRICTED_GUEST |
SECONDARY_EXEC_PAUSE_LOOP_EXITING |
SECONDARY_EXEC_RDTSCP |
- SECONDARY_EXEC_ENABLE_INVPCID;
+ SECONDARY_EXEC_ENABLE_INVPCID |
+ SECONDARY_EXEC_APIC_REGISTER_VIRT;
if (adjust_vmx_controls(min2, opt2,
MSR_IA32_VMX_PROCBASED_CTLS2,
&_cpu_based_2nd_exec_control) < 0)
@@ -2509,6 +2519,11 @@ static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
_cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
#endif
+
+ if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
+ _cpu_based_2nd_exec_control &= ~(
+ SECONDARY_EXEC_APIC_REGISTER_VIRT);
+
if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
/* CR3 accesses and invlpg don't need to cause VM Exits when EPT
enabled */
@@ -2706,6 +2721,9 @@ static __init int hardware_setup(void)
if (!cpu_has_vmx_ple())
ple_gap = 0;
+ if (!cpu_has_vmx_apic_register_virt())
+ enable_apicv_reg_vid = 0;
+
if (nested)
nested_vmx_setup_ctls_msrs();
@@ -3819,6 +3837,8 @@ static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
if (!ple_gap)
exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
+ if (!enable_apicv_reg_vid)
+ exec_control &= ~SECONDARY_EXEC_APIC_REGISTER_VIRT;
return exec_control;
}
@@ -4786,6 +4806,16 @@ static int handle_apic_access(struct kvm_vcpu *vcpu)
return emulate_instruction(vcpu, 0) == EMULATE_DONE;
}
+static int handle_apic_write(struct kvm_vcpu *vcpu)
+{
+ unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
+ u32 offset = exit_qualification & 0xfff;
+
+ /* APIC-write VM exit is trap-like and thus no need to adjust IP */
+ kvm_apic_write_nodecode(vcpu, offset);
+ return 1;
+}
+
static int handle_task_switch(struct kvm_vcpu *vcpu)
{
struct vcpu_vmx *vmx = to_vmx(vcpu);
@@ -5725,6 +5755,7 @@ static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
[EXIT_REASON_VMON] = handle_vmon,
[EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
[EXIT_REASON_APIC_ACCESS] = handle_apic_access,
+ [EXIT_REASON_APIC_WRITE] = handle_apic_write,
[EXIT_REASON_WBINVD] = handle_wbinvd,
[EXIT_REASON_XSETBV] = handle_xsetbv,
[EXIT_REASON_TASK_SWITCH] = handle_task_switch,
--
1.7.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v6 2/3] x86, apicv: add virtual interrupt delivery support
2012-12-12 4:56 [PATCH v6 0/3] x86, apicv: Add APIC virtualization support Yang Zhang
2012-12-12 4:56 ` [PATCH v6 1/3] x86, apicv: add APICv register " Yang Zhang
@ 2012-12-12 4:56 ` Yang Zhang
2012-12-12 10:54 ` Gleb Natapov
2012-12-12 4:56 ` [PATCH v6 3/3] x86, apicv: add virtual x2apic support Yang Zhang
2 siblings, 1 reply; 7+ messages in thread
From: Yang Zhang @ 2012-12-12 4:56 UTC (permalink / raw)
To: kvm; +Cc: mtosatti, gleb, haitao.shan, Yang Zhang, Kevin Tian, Yang Zhang
From: Yang Zhang <yang.z.zhang@Intel.com>
Virtual interrupt delivery avoids KVM to inject vAPIC interrupts
manually, which is fully taken care of by the hardware. This needs
some special awareness into existing interrupr injection path:
- for pending interrupt, instead of direct injection, we may need
update architecture specific indicators before resuming to guest.
- A pending interrupt, which is masked by ISR, should be also
considered in above update action, since hardware will decide
when to inject it at right time. Current has_interrupt and
get_interrupt only returns a valid vector from injection p.o.v.
Signed-off-by: Kevin Tian <kevin.tian@intel.com>
Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>
---
arch/ia64/kvm/lapic.h | 6 ++
arch/x86/include/asm/kvm_host.h | 5 ++
arch/x86/include/asm/vmx.h | 11 ++++
arch/x86/kvm/irq.c | 60 +++++++++++++++++++---
arch/x86/kvm/lapic.c | 99 +++++++++++++++++++++++++++++++++---
arch/x86/kvm/lapic.h | 9 +++
arch/x86/kvm/svm.c | 25 +++++++++
arch/x86/kvm/vmx.c | 106 +++++++++++++++++++++++++++++++++++++--
arch/x86/kvm/x86.c | 11 +++-
include/linux/kvm_host.h | 2 +
virt/kvm/ioapic.c | 33 ++++++++++++
virt/kvm/ioapic.h | 1 +
virt/kvm/irq_comm.c | 20 +++++++
13 files changed, 365 insertions(+), 23 deletions(-)
diff --git a/arch/ia64/kvm/lapic.h b/arch/ia64/kvm/lapic.h
index c5f92a9..cb59eb4 100644
--- a/arch/ia64/kvm/lapic.h
+++ b/arch/ia64/kvm/lapic.h
@@ -27,4 +27,10 @@ int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq);
#define kvm_apic_present(x) (true)
#define kvm_lapic_enabled(x) (true)
+static inline void kvm_update_eoi_exitmap(struct kvm *kvm,
+ struct kvm_lapic_irq *irq)
+{
+ /* IA64 has no apicv supporting, do nothing here */
+}
+
#endif
diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
index dc87b65..d49b361 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -697,6 +697,10 @@ struct kvm_x86_ops {
void (*enable_nmi_window)(struct kvm_vcpu *vcpu);
void (*enable_irq_window)(struct kvm_vcpu *vcpu);
void (*update_cr8_intercept)(struct kvm_vcpu *vcpu, int tpr, int irr);
+ int (*has_virtual_interrupt_delivery)(struct kvm_vcpu *vcpu);
+ void (*update_apic_irq)(struct kvm_vcpu *vcpu, int max_irr);
+ void (*update_eoi_exitmap)(struct kvm_vcpu *vcpu, u32 vector, bool set);
+ void (*load_eoi_exitmap)(struct kvm_vcpu *vcpu);
int (*set_tss_addr)(struct kvm *kvm, unsigned int addr);
int (*get_tdp_level)(void);
u64 (*get_mt_mask)(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio);
@@ -991,6 +995,7 @@ int kvm_age_hva(struct kvm *kvm, unsigned long hva);
int kvm_test_age_hva(struct kvm *kvm, unsigned long hva);
void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
int cpuid_maxphyaddr(struct kvm_vcpu *vcpu);
+int kvm_cpu_has_injectable_intr(struct kvm_vcpu *v);
int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu);
int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu);
int kvm_cpu_get_interrupt(struct kvm_vcpu *v);
diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h
index 21101b6..1003341 100644
--- a/arch/x86/include/asm/vmx.h
+++ b/arch/x86/include/asm/vmx.h
@@ -62,6 +62,7 @@
#define EXIT_REASON_MCE_DURING_VMENTRY 41
#define EXIT_REASON_TPR_BELOW_THRESHOLD 43
#define EXIT_REASON_APIC_ACCESS 44
+#define EXIT_REASON_EOI_INDUCED 45
#define EXIT_REASON_EPT_VIOLATION 48
#define EXIT_REASON_EPT_MISCONFIG 49
#define EXIT_REASON_WBINVD 54
@@ -143,6 +144,7 @@
#define SECONDARY_EXEC_WBINVD_EXITING 0x00000040
#define SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080
#define SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100
+#define SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200
#define SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400
#define SECONDARY_EXEC_ENABLE_INVPCID 0x00001000
@@ -180,6 +182,7 @@ enum vmcs_field {
GUEST_GS_SELECTOR = 0x0000080a,
GUEST_LDTR_SELECTOR = 0x0000080c,
GUEST_TR_SELECTOR = 0x0000080e,
+ GUEST_INTR_STATUS = 0x00000810,
HOST_ES_SELECTOR = 0x00000c00,
HOST_CS_SELECTOR = 0x00000c02,
HOST_SS_SELECTOR = 0x00000c04,
@@ -207,6 +210,14 @@ enum vmcs_field {
APIC_ACCESS_ADDR_HIGH = 0x00002015,
EPT_POINTER = 0x0000201a,
EPT_POINTER_HIGH = 0x0000201b,
+ EOI_EXIT_BITMAP0 = 0x0000201c,
+ EOI_EXIT_BITMAP0_HIGH = 0x0000201d,
+ EOI_EXIT_BITMAP1 = 0x0000201e,
+ EOI_EXIT_BITMAP1_HIGH = 0x0000201f,
+ EOI_EXIT_BITMAP2 = 0x00002020,
+ EOI_EXIT_BITMAP2_HIGH = 0x00002021,
+ EOI_EXIT_BITMAP3 = 0x00002022,
+ EOI_EXIT_BITMAP3_HIGH = 0x00002023,
GUEST_PHYSICAL_ADDRESS = 0x00002400,
GUEST_PHYSICAL_ADDRESS_HIGH = 0x00002401,
VMCS_LINK_POINTER = 0x00002800,
diff --git a/arch/x86/kvm/irq.c b/arch/x86/kvm/irq.c
index ebd98d0..537ce4b 100644
--- a/arch/x86/kvm/irq.c
+++ b/arch/x86/kvm/irq.c
@@ -38,37 +38,81 @@ int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
EXPORT_SYMBOL(kvm_cpu_has_pending_timer);
/*
+ * check if there is pending interrupt from
+ * non-APIC source without intack.
+ */
+static int kvm_cpu_has_extint(struct kvm_vcpu *v)
+{
+ if (kvm_apic_accept_pic_intr(v))
+ return pic_irqchip(v->kvm)->output; /* PIC */
+ else
+ return 0;
+}
+
+/*
+ * check if there is injectable interrupt:
+ * when virtual interrupt delivery enabled,
+ * interrupt from apic will handled by hardware,
+ * we don't need to check it here.
+ */
+int kvm_cpu_has_injectable_intr(struct kvm_vcpu *v)
+{
+ if (!irqchip_in_kernel(v->kvm))
+ return v->arch.interrupt.pending;
+
+ if (kvm_cpu_has_extint(v))
+ return 1;
+ else if (!kvm_apic_vid_enabled(v))
+ return kvm_apic_has_interrupt(v) != -1; /* LAPIC */
+
+ return 0;
+}
+
+/*
* check if there is pending interrupt without
* intack.
*/
int kvm_cpu_has_interrupt(struct kvm_vcpu *v)
{
- struct kvm_pic *s;
-
if (!irqchip_in_kernel(v->kvm))
return v->arch.interrupt.pending;
- if (kvm_apic_accept_pic_intr(v) && pic_irqchip(v->kvm)->output)
- return pic_irqchip(v->kvm)->output; /* PIC */
+ if (kvm_cpu_has_extint(v))
+ return 1;
return kvm_apic_has_interrupt(v) != -1; /* LAPIC */
}
EXPORT_SYMBOL_GPL(kvm_cpu_has_interrupt);
/*
+ * Read pending interrupt(from non-APIC source)
+ * vector and intack.
+ */
+static int kvm_cpu_get_extint(struct kvm_vcpu *v)
+{
+ if (kvm_cpu_has_extint(v))
+ return kvm_pic_read_irq(v->kvm); /* PIC */
+ return -1;
+}
+
+/*
* Read pending interrupt vector and intack.
*/
int kvm_cpu_get_interrupt(struct kvm_vcpu *v)
{
- struct kvm_pic *s;
+ int vector;
if (!irqchip_in_kernel(v->kvm))
return v->arch.interrupt.nr;
- if (kvm_apic_accept_pic_intr(v) && pic_irqchip(v->kvm)->output)
- return kvm_pic_read_irq(v->kvm); /* PIC */
+ vector = kvm_cpu_get_extint(v);
+
+ if (kvm_apic_vid_enabled(v))
+ return vector; /* PIC */
+ else if (vector == -1)
+ vector = kvm_get_apic_interrupt(v); /* APIC */
- return kvm_get_apic_interrupt(v); /* APIC */
+ return vector;
}
EXPORT_SYMBOL_GPL(kvm_cpu_get_interrupt);
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index 0664c13..0dfbd47 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -236,12 +236,14 @@ static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id)
{
apic_set_reg(apic, APIC_ID, id << 24);
recalculate_apic_map(apic->vcpu->kvm);
+ ioapic_update_eoi_exitmap(apic->vcpu->kvm);
}
static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
{
apic_set_reg(apic, APIC_LDR, id);
recalculate_apic_map(apic->vcpu->kvm);
+ ioapic_update_eoi_exitmap(apic->vcpu->kvm);
}
static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
@@ -577,6 +579,63 @@ int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
return result;
}
+static void kvm_apic_update_eoi_exitmap(struct kvm_vcpu *vcpu,
+ u32 vector, bool set)
+{
+ kvm_x86_ops->update_eoi_exitmap(vcpu, vector, set);
+}
+
+void kvm_update_eoi_exitmap(struct kvm *kvm, struct kvm_lapic_irq *irq)
+{
+ struct kvm_vcpu *vcpu;
+ struct kvm_lapic **dst;
+ struct kvm_apic_map *map;
+ unsigned long bitmap = 1;
+ bool set;
+ int i;
+ DECLARE_BITMAP(vcpu_map, KVM_MAX_VCPUS);
+
+ bitmap_zero(vcpu_map, 255);
+
+ rcu_read_lock();
+ map = rcu_dereference(kvm->arch.apic_map);
+
+ if (unlikely(!map)) {
+ bitmap_fill(vcpu_map, 255);
+ goto out;
+ }
+
+ if (irq->dest_mode == 0) { /* physical mode */
+ if (irq->delivery_mode == APIC_DM_LOWEST ||
+ irq->dest_id == 0xff) {
+ bitmap_fill(vcpu_map, 255);
+ goto out;
+ }
+ dst = &map->phys_map[irq->dest_id & 0xff];
+ } else {
+ u32 mda = irq->dest_id << (32 - map->ldr_bits);
+
+ dst = map->logical_map[apic_cluster_id(map, mda)];
+
+ bitmap = apic_logical_id(map, mda);
+ }
+
+ for_each_set_bit(i, &bitmap, 16) {
+ if (!dst[i])
+ continue;
+ set_bit(dst[i]->vcpu->vcpu_id, vcpu_map);
+ }
+
+out:
+ rcu_read_unlock();
+ kvm_for_each_vcpu(i, vcpu, kvm) {
+ if (!kvm_apic_present(vcpu))
+ continue;
+ set = test_bit(vcpu->vcpu_id, vcpu_map);
+ kvm_apic_update_eoi_exitmap(vcpu, irq->vector, set);
+ }
+
+}
bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
struct kvm_lapic_irq *irq, int *r)
{
@@ -740,6 +799,19 @@ int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
}
+static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
+{
+ if (!(kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI) &&
+ kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) {
+ int trigger_mode;
+ if (apic_test_vector(vector, apic->regs + APIC_TMR))
+ trigger_mode = IOAPIC_LEVEL_TRIG;
+ else
+ trigger_mode = IOAPIC_EDGE_TRIG;
+ kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
+ }
+}
+
static int apic_set_eoi(struct kvm_lapic *apic)
{
int vector = apic_find_highest_isr(apic);
@@ -756,19 +828,26 @@ static int apic_set_eoi(struct kvm_lapic *apic)
apic_clear_isr(vector, apic);
apic_update_ppr(apic);
- if (!(kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI) &&
- kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) {
- int trigger_mode;
- if (apic_test_vector(vector, apic->regs + APIC_TMR))
- trigger_mode = IOAPIC_LEVEL_TRIG;
- else
- trigger_mode = IOAPIC_EDGE_TRIG;
- kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
- }
+ kvm_ioapic_send_eoi(apic, vector);
kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
return vector;
}
+/*
+ * this interface assumes a trap-like exit, which has already finished
+ * desired side effect including vISR and vPPR update.
+ */
+void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
+{
+ struct kvm_lapic *apic = vcpu->arch.apic;
+
+ trace_kvm_eoi(apic, vector);
+
+ kvm_ioapic_send_eoi(apic, vector);
+ kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
+}
+EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
+
static void apic_send_ipi(struct kvm_lapic *apic)
{
u32 icr_low = kvm_apic_get_reg(apic, APIC_ICR);
@@ -1071,6 +1150,7 @@ static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
if (!apic_x2apic_mode(apic)) {
apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
recalculate_apic_map(apic->vcpu->kvm);
+ ioapic_update_eoi_exitmap(apic->vcpu->kvm);
} else
ret = 1;
break;
@@ -1318,6 +1398,7 @@ void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
else
static_key_slow_inc(&apic_hw_disabled.key);
recalculate_apic_map(vcpu->kvm);
+ ioapic_update_eoi_exitmap(apic->vcpu->kvm);
}
if (!kvm_vcpu_is_bsp(apic->vcpu))
diff --git a/arch/x86/kvm/lapic.h b/arch/x86/kvm/lapic.h
index 9a8ee22..cf16ecb 100644
--- a/arch/x86/kvm/lapic.h
+++ b/arch/x86/kvm/lapic.h
@@ -39,6 +39,7 @@ void kvm_free_lapic(struct kvm_vcpu *vcpu);
int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu);
int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu);
int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu);
+int kvm_apic_get_highest_irr(struct kvm_vcpu *vcpu);
void kvm_lapic_reset(struct kvm_vcpu *vcpu);
u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu);
void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8);
@@ -55,6 +56,8 @@ int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type);
bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
struct kvm_lapic_irq *irq, int *r);
+void kvm_update_eoi_exitmap(struct kvm *kvm, struct kvm_lapic_irq *irq);
+
u64 kvm_get_apic_base(struct kvm_vcpu *vcpu);
void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data);
void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
@@ -65,6 +68,7 @@ u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu);
void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data);
void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset);
+void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector);
void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr);
void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu);
@@ -126,4 +130,9 @@ static inline int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
return kvm_apic_present(vcpu) && kvm_apic_sw_enabled(vcpu->arch.apic);
}
+static inline bool kvm_apic_vid_enabled(struct kvm_vcpu *vcpu)
+{
+ return kvm_x86_ops->has_virtual_interrupt_delivery(vcpu);
+}
+
#endif
diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index dcb7952..b501d5a 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -3573,6 +3573,27 @@ static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
}
+static int svm_has_virtual_interrupt_delivery(struct kvm_vcpu *vcpu)
+{
+ return 0;
+}
+
+static void svm_update_apic_irq(struct kvm_vcpu *vcpu, int max_irr)
+{
+ return ;
+}
+
+static void svm_update_eoi_exitmap(struct kvm_vcpu *vcpu,
+ u32 vector, bool set)
+{
+ return ;
+}
+
+static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu)
+{
+ return ;
+}
+
static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
{
struct vcpu_svm *svm = to_svm(vcpu);
@@ -4292,6 +4313,10 @@ static struct kvm_x86_ops svm_x86_ops = {
.enable_nmi_window = enable_nmi_window,
.enable_irq_window = enable_irq_window,
.update_cr8_intercept = update_cr8_intercept,
+ .has_virtual_interrupt_delivery = svm_has_virtual_interrupt_delivery,
+ .update_apic_irq = svm_update_apic_irq;
+ .update_eoi_exitmap = svm_update_eoi_exitmap;
+ .load_eoi_exitmap = svm_load_eoi_exitmap,
.set_tss_addr = svm_set_tss_addr,
.get_tdp_level = get_npt_level,
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index 4838e4f..f0ed77c 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -432,6 +432,8 @@ struct vcpu_vmx {
bool rdtscp_enabled;
+ unsigned long eoi_exit_bitmap[4];
+
/* Support for a guest hypervisor (nested VMX) */
struct nested_vmx nested;
};
@@ -770,6 +772,12 @@ static inline bool cpu_has_vmx_apic_register_virt(void)
SECONDARY_EXEC_APIC_REGISTER_VIRT;
}
+static inline bool cpu_has_vmx_virtual_intr_delivery(void)
+{
+ return vmcs_config.cpu_based_2nd_exec_ctrl &
+ SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
+}
+
static inline bool cpu_has_vmx_flexpriority(void)
{
return cpu_has_vmx_tpr_shadow() &&
@@ -2508,7 +2516,8 @@ static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
SECONDARY_EXEC_PAUSE_LOOP_EXITING |
SECONDARY_EXEC_RDTSCP |
SECONDARY_EXEC_ENABLE_INVPCID |
- SECONDARY_EXEC_APIC_REGISTER_VIRT;
+ SECONDARY_EXEC_APIC_REGISTER_VIRT |
+ SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
if (adjust_vmx_controls(min2, opt2,
MSR_IA32_VMX_PROCBASED_CTLS2,
&_cpu_based_2nd_exec_control) < 0)
@@ -2522,7 +2531,8 @@ static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
_cpu_based_2nd_exec_control &= ~(
- SECONDARY_EXEC_APIC_REGISTER_VIRT);
+ SECONDARY_EXEC_APIC_REGISTER_VIRT |
+ SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
/* CR3 accesses and invlpg don't need to cause VM Exits when EPT
@@ -2721,9 +2731,15 @@ static __init int hardware_setup(void)
if (!cpu_has_vmx_ple())
ple_gap = 0;
- if (!cpu_has_vmx_apic_register_virt())
+ if (!cpu_has_vmx_apic_register_virt() ||
+ !cpu_has_vmx_virtual_intr_delivery())
enable_apicv_reg_vid = 0;
+ if (enable_apicv_reg_vid)
+ kvm_x86_ops->update_cr8_intercept = NULL;
+ else
+ kvm_x86_ops->update_apic_irq = NULL;
+
if (nested)
nested_vmx_setup_ctls_msrs();
@@ -3838,7 +3854,8 @@ static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
if (!ple_gap)
exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
if (!enable_apicv_reg_vid)
- exec_control &= ~SECONDARY_EXEC_APIC_REGISTER_VIRT;
+ exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
+ SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
return exec_control;
}
@@ -3883,6 +3900,15 @@ static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
vmx_secondary_exec_control(vmx));
}
+ if (enable_apicv_reg_vid) {
+ vmcs_write64(EOI_EXIT_BITMAP0, 0);
+ vmcs_write64(EOI_EXIT_BITMAP1, 0);
+ vmcs_write64(EOI_EXIT_BITMAP2, 0);
+ vmcs_write64(EOI_EXIT_BITMAP3, 0);
+
+ vmcs_write16(GUEST_INTR_STATUS, 0);
+ }
+
if (ple_gap) {
vmcs_write32(PLE_GAP, ple_gap);
vmcs_write32(PLE_WINDOW, ple_window);
@@ -4806,6 +4832,16 @@ static int handle_apic_access(struct kvm_vcpu *vcpu)
return emulate_instruction(vcpu, 0) == EMULATE_DONE;
}
+static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
+{
+ unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
+ int vector = exit_qualification & 0xff;
+
+ /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
+ kvm_apic_set_eoi_accelerated(vcpu, vector);
+ return 1;
+}
+
static int handle_apic_write(struct kvm_vcpu *vcpu)
{
unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
@@ -5756,6 +5792,7 @@ static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
[EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
[EXIT_REASON_APIC_ACCESS] = handle_apic_access,
[EXIT_REASON_APIC_WRITE] = handle_apic_write,
+ [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
[EXIT_REASON_WBINVD] = handle_wbinvd,
[EXIT_REASON_XSETBV] = handle_xsetbv,
[EXIT_REASON_TASK_SWITCH] = handle_task_switch,
@@ -6105,6 +6142,63 @@ static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
vmcs_write32(TPR_THRESHOLD, irr);
}
+static int vmx_has_virtual_interrupt_delivery(struct kvm_vcpu *vcpu)
+{
+ return enable_apicv_reg_vid;
+}
+
+static void vmx_update_rvi(int vector)
+{
+ u16 status;
+ u8 old;
+
+ status = vmcs_read16(GUEST_INTR_STATUS);
+ old = (u8)status & 0xff;
+ if ((u8)vector != old) {
+ status &= ~0xff;
+ status |= (u8)vector;
+ vmcs_write16(GUEST_INTR_STATUS, status);
+ }
+}
+
+static void vmx_update_apic_irq(struct kvm_vcpu *vcpu, int max_irr)
+{
+ if (!enable_apicv_reg_vid || max_irr == -1)
+ return ;
+
+ vmx_update_rvi(max_irr);
+}
+
+static void vmx_update_eoi_exitmap(struct kvm_vcpu *vcpu,
+ u32 vector, bool set)
+{
+ struct vcpu_vmx *vmx = to_vmx(vcpu);
+
+ if (!enable_apicv_reg_vid)
+ return ;
+
+ if (WARN_ONCE((vector > 255),
+ "KVM VMX: vector (%d) out of range\n", vector))
+ return;
+
+ if (set)
+ set_bit(vector, vmx->eoi_exit_bitmap);
+ else
+ clear_bit(vector, vmx->eoi_exit_bitmap);
+
+ kvm_make_request(KVM_REQ_EOIBITMAP, vcpu);
+}
+
+static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu)
+{
+ struct vcpu_vmx *vmx = to_vmx(vcpu);
+
+ vmcs_write64(EOI_EXIT_BITMAP0, vmx->eoi_exit_bitmap[0]);
+ vmcs_write64(EOI_EXIT_BITMAP1, vmx->eoi_exit_bitmap[1]);
+ vmcs_write64(EOI_EXIT_BITMAP2, vmx->eoi_exit_bitmap[2]);
+ vmcs_write64(EOI_EXIT_BITMAP3, vmx->eoi_exit_bitmap[3]);
+}
+
static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
{
u32 exit_intr_info;
@@ -7365,6 +7459,10 @@ static struct kvm_x86_ops vmx_x86_ops = {
.enable_nmi_window = enable_nmi_window,
.enable_irq_window = enable_irq_window,
.update_cr8_intercept = update_cr8_intercept,
+ .has_virtual_interrupt_delivery = vmx_has_virtual_interrupt_delivery,
+ .update_apic_irq = vmx_update_apic_irq,
+ .update_eoi_exitmap = vmx_update_eoi_exitmap,
+ .load_eoi_exitmap = vmx_load_eoi_exitmap,
.set_tss_addr = vmx_set_tss_addr,
.get_tdp_level = get_ept_level,
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 3bdaf29..da3c6d6 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -5534,7 +5534,7 @@ static void inject_pending_event(struct kvm_vcpu *vcpu)
vcpu->arch.nmi_injected = true;
kvm_x86_ops->set_nmi(vcpu);
}
- } else if (kvm_cpu_has_interrupt(vcpu)) {
+ } else if (kvm_cpu_has_injectable_intr(vcpu)) {
if (kvm_x86_ops->interrupt_allowed(vcpu)) {
kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
false);
@@ -5655,6 +5655,8 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
kvm_handle_pmu_event(vcpu);
if (kvm_check_request(KVM_REQ_PMI, vcpu))
kvm_deliver_pmi(vcpu);
+ if (kvm_check_request(KVM_REQ_EOIBITMAP, vcpu))
+ kvm_x86_ops->load_eoi_exitmap(vcpu);
}
if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
@@ -5663,10 +5665,15 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
/* enable NMI/IRQ window open exits if needed */
if (vcpu->arch.nmi_pending)
kvm_x86_ops->enable_nmi_window(vcpu);
- else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
+ else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
kvm_x86_ops->enable_irq_window(vcpu);
if (kvm_lapic_enabled(vcpu)) {
+ /* update archtecture specific hints for APIC
+ * virtual interrupt delivery */
+ if (kvm_x86_ops->update_apic_irq)
+ kvm_x86_ops->update_apic_irq(vcpu,
+ kvm_lapic_find_highest_irr(vcpu));
update_cr8_intercept(vcpu);
kvm_lapic_sync_to_vapic(vcpu);
}
diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h
index 8e5c7b6..8ba5057 100644
--- a/include/linux/kvm_host.h
+++ b/include/linux/kvm_host.h
@@ -133,6 +133,7 @@ static inline bool is_error_page(struct page *page)
#define KVM_REQ_WATCHDOG 18
#define KVM_REQ_MASTERCLOCK_UPDATE 19
#define KVM_REQ_MCLOCK_INPROGRESS 20
+#define KVM_REQ_EOIBITMAP 21
#define KVM_USERSPACE_IRQ_SOURCE_ID 0
#define KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID 1
@@ -695,6 +696,7 @@ void kvm_get_intr_delivery_bitmask(struct kvm_ioapic *ioapic,
int kvm_set_irq(struct kvm *kvm, int irq_source_id, u32 irq, int level);
int kvm_set_msi(struct kvm_kernel_irq_routing_entry *irq_entry, struct kvm *kvm,
int irq_source_id, int level);
+bool kvm_irq_has_notifier(struct kvm *kvm, unsigned irqchip, unsigned pin);
void kvm_notify_acked_irq(struct kvm *kvm, unsigned irqchip, unsigned pin);
void kvm_register_irq_ack_notifier(struct kvm *kvm,
struct kvm_irq_ack_notifier *kian);
diff --git a/virt/kvm/ioapic.c b/virt/kvm/ioapic.c
index cfb7e4d..7c8d9e0 100644
--- a/virt/kvm/ioapic.c
+++ b/virt/kvm/ioapic.c
@@ -115,6 +115,37 @@ static void update_handled_vectors(struct kvm_ioapic *ioapic)
smp_wmb();
}
+static void ioapic_update_eoi_exitmap_one(struct kvm_ioapic *ioapic, int pin)
+{
+ union kvm_ioapic_redirect_entry *e;
+
+ e = &ioapic->redirtbl[pin];
+
+ if ((e->fields.trig_mode == IOAPIC_LEVEL_TRIG ||
+ kvm_irq_has_notifier(ioapic->kvm, KVM_IRQCHIP_IOAPIC, pin))) {
+ struct kvm_lapic_irq irqe;
+
+ irqe.dest_id = e->fields.dest_id;
+ irqe.vector = e->fields.vector;
+ irqe.dest_mode = e->fields.dest_mode;
+ irqe.delivery_mode = e->fields.delivery_mode << 8;
+ kvm_update_eoi_exitmap(ioapic->kvm, &irqe);
+ }
+}
+
+void ioapic_update_eoi_exitmap(struct kvm *kvm)
+{
+ struct kvm_ioapic *ioapic = kvm->arch.vioapic;
+ union kvm_ioapic_redirect_entry *e;
+ int index;
+
+ for (index = 0; index < IOAPIC_NUM_PINS; index++) {
+ e = &ioapic->redirtbl[index];
+ if (!e->fields.mask)
+ ioapic_update_eoi_exitmap_one(ioapic, index);
+ }
+}
+
static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
{
unsigned index;
@@ -156,6 +187,8 @@ static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG
&& ioapic->irr & (1 << index))
ioapic_service(ioapic, index);
+ if (!e->fields.mask)
+ ioapic_update_eoi_exitmap_one(ioapic, index);
break;
}
}
diff --git a/virt/kvm/ioapic.h b/virt/kvm/ioapic.h
index a30abfe..e8d67cf 100644
--- a/virt/kvm/ioapic.h
+++ b/virt/kvm/ioapic.h
@@ -82,5 +82,6 @@ int kvm_irq_delivery_to_apic(struct kvm *kvm, struct kvm_lapic *src,
struct kvm_lapic_irq *irq);
int kvm_get_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state);
int kvm_set_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state);
+void ioapic_update_eoi_exitmap(struct kvm *kvm);
#endif
diff --git a/virt/kvm/irq_comm.c b/virt/kvm/irq_comm.c
index 2eb58af..0ac691f 100644
--- a/virt/kvm/irq_comm.c
+++ b/virt/kvm/irq_comm.c
@@ -178,6 +178,24 @@ int kvm_set_irq(struct kvm *kvm, int irq_source_id, u32 irq, int level)
return ret;
}
+bool kvm_irq_has_notifier(struct kvm *kvm, unsigned irqchip, unsigned pin)
+{
+ struct kvm_irq_ack_notifier *kian;
+ struct hlist_node *n;
+ int gsi;
+
+ rcu_read_lock();
+ gsi = rcu_dereference(kvm->irq_routing)->chip[irqchip][pin];
+ if (gsi != -1)
+ hlist_for_each_entry_rcu(kian, n, &kvm->irq_ack_notifier_list,
+ link)
+ if (kian->gsi == gsi)
+ return true;
+ rcu_read_unlock();
+
+ return false;
+}
+
void kvm_notify_acked_irq(struct kvm *kvm, unsigned irqchip, unsigned pin)
{
struct kvm_irq_ack_notifier *kian;
@@ -202,6 +220,7 @@ void kvm_register_irq_ack_notifier(struct kvm *kvm,
mutex_lock(&kvm->irq_lock);
hlist_add_head_rcu(&kian->link, &kvm->irq_ack_notifier_list);
mutex_unlock(&kvm->irq_lock);
+ ioapic_update_eoi_exitmap(kvm);
}
void kvm_unregister_irq_ack_notifier(struct kvm *kvm,
@@ -211,6 +230,7 @@ void kvm_unregister_irq_ack_notifier(struct kvm *kvm,
hlist_del_init_rcu(&kian->link);
mutex_unlock(&kvm->irq_lock);
synchronize_rcu();
+ ioapic_update_eoi_exitmap(kvm);
}
int kvm_request_irq_source_id(struct kvm *kvm)
--
1.7.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v6 3/3] x86, apicv: add virtual x2apic support
2012-12-12 4:56 [PATCH v6 0/3] x86, apicv: Add APIC virtualization support Yang Zhang
2012-12-12 4:56 ` [PATCH v6 1/3] x86, apicv: add APICv register " Yang Zhang
2012-12-12 4:56 ` [PATCH v6 2/3] x86, apicv: add virtual interrupt delivery support Yang Zhang
@ 2012-12-12 4:56 ` Yang Zhang
2 siblings, 0 replies; 7+ messages in thread
From: Yang Zhang @ 2012-12-12 4:56 UTC (permalink / raw)
To: kvm; +Cc: mtosatti, gleb, haitao.shan, Yang Zhang, Kevin Tian
basically to benefit from apicv, we need clear MSR bitmap for
corresponding x2apic MSRs:
0x800 - 0x8ff: no read intercept for apicv register virtualization
TPR,EOI,SELF-IPI: no write intercept for virtual interrupt delivery
Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>
Signed-off-by: Kevin Tian <kevin.tian@intel.com>
---
arch/x86/kvm/vmx.c | 62 ++++++++++++++++++++++++++++++++++++++++++++++------
1 files changed, 55 insertions(+), 7 deletions(-)
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index f0ed77c..bc1439b 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -3731,7 +3731,10 @@ static void free_vpid(struct vcpu_vmx *vmx)
spin_unlock(&vmx_vpid_lock);
}
-static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
+#define MSR_TYPE_R 1
+#define MSR_TYPE_W 2
+static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
+ u32 msr, int type)
{
int f = sizeof(unsigned long);
@@ -3744,20 +3747,52 @@ static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
* We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
*/
if (msr <= 0x1fff) {
- __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
- __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
+ if (type & MSR_TYPE_R)
+ /* read-low */
+ __clear_bit(msr, msr_bitmap + 0x000 / f);
+
+ if (type & MSR_TYPE_W)
+ /* write-low */
+ __clear_bit(msr, msr_bitmap + 0x800 / f);
+
} else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
msr &= 0x1fff;
- __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
- __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
+ if (type & MSR_TYPE_R)
+ /* read-high */
+ __clear_bit(msr, msr_bitmap + 0x400 / f);
+
+ if (type & MSR_TYPE_W)
+ /* write-high */
+ __clear_bit(msr, msr_bitmap + 0xc00 / f);
+
}
}
static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
{
if (!longmode_only)
- __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
- __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
+ __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
+ msr, MSR_TYPE_R | MSR_TYPE_W);
+ __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
+ msr, MSR_TYPE_R | MSR_TYPE_W);
+}
+
+static void vmx_disable_intercept_for_msr_read(u32 msr, bool longmode_only)
+{
+ if (!longmode_only)
+ __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
+ msr, MSR_TYPE_R);
+ __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
+ msr, MSR_TYPE_R);
+}
+
+static void vmx_disable_intercept_for_msr_write(u32 msr, bool longmode_only)
+{
+ if (!longmode_only)
+ __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
+ msr, MSR_TYPE_W);
+ __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
+ msr, MSR_TYPE_W);
}
/*
@@ -7548,6 +7583,19 @@ static int __init vmx_init(void)
vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
+ if (enable_apicv_reg_vid) {
+ int msr;
+ for (msr = 0x800; msr <= 0x8ff; msr++)
+ vmx_disable_intercept_for_msr_read(msr, false);
+
+ /* TPR */
+ vmx_disable_intercept_for_msr_write(0x808, false);
+ /* EOI */
+ vmx_disable_intercept_for_msr_write(0x80b, false);
+ /* SELF-IPI */
+ vmx_disable_intercept_for_msr_write(0x83f, false);
+ }
+
if (enable_ept) {
kvm_mmu_set_mask_ptes(0ull,
(enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
--
1.7.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v6 2/3] x86, apicv: add virtual interrupt delivery support
2012-12-12 4:56 ` [PATCH v6 2/3] x86, apicv: add virtual interrupt delivery support Yang Zhang
@ 2012-12-12 10:54 ` Gleb Natapov
2012-12-13 1:09 ` Zhang, Yang Z
0 siblings, 1 reply; 7+ messages in thread
From: Gleb Natapov @ 2012-12-12 10:54 UTC (permalink / raw)
To: Yang Zhang; +Cc: kvm, mtosatti, haitao.shan, Kevin Tian
On Wed, Dec 12, 2012 at 12:56:47PM +0800, Yang Zhang wrote:
> From: Yang Zhang <yang.z.zhang@Intel.com>
>
> Virtual interrupt delivery avoids KVM to inject vAPIC interrupts
> manually, which is fully taken care of by the hardware. This needs
> some special awareness into existing interrupr injection path:
>
> - for pending interrupt, instead of direct injection, we may need
> update architecture specific indicators before resuming to guest.
>
> - A pending interrupt, which is masked by ISR, should be also
> considered in above update action, since hardware will decide
> when to inject it at right time. Current has_interrupt and
> get_interrupt only returns a valid vector from injection p.o.v.
>
> Signed-off-by: Kevin Tian <kevin.tian@intel.com>
> Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>
> ---
> arch/ia64/kvm/lapic.h | 6 ++
> arch/x86/include/asm/kvm_host.h | 5 ++
> arch/x86/include/asm/vmx.h | 11 ++++
> arch/x86/kvm/irq.c | 60 +++++++++++++++++++---
> arch/x86/kvm/lapic.c | 99 +++++++++++++++++++++++++++++++++---
> arch/x86/kvm/lapic.h | 9 +++
> arch/x86/kvm/svm.c | 25 +++++++++
> arch/x86/kvm/vmx.c | 106 +++++++++++++++++++++++++++++++++++++--
> arch/x86/kvm/x86.c | 11 +++-
> include/linux/kvm_host.h | 2 +
> virt/kvm/ioapic.c | 33 ++++++++++++
> virt/kvm/ioapic.h | 1 +
> virt/kvm/irq_comm.c | 20 +++++++
> 13 files changed, 365 insertions(+), 23 deletions(-)
>
> diff --git a/arch/ia64/kvm/lapic.h b/arch/ia64/kvm/lapic.h
> index c5f92a9..cb59eb4 100644
> --- a/arch/ia64/kvm/lapic.h
> +++ b/arch/ia64/kvm/lapic.h
> @@ -27,4 +27,10 @@ int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq);
> #define kvm_apic_present(x) (true)
> #define kvm_lapic_enabled(x) (true)
>
> +static inline void kvm_update_eoi_exitmap(struct kvm *kvm,
> + struct kvm_lapic_irq *irq)
> +{
> + /* IA64 has no apicv supporting, do nothing here */
> +}
> +
> #endif
> diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
> index dc87b65..d49b361 100644
> --- a/arch/x86/include/asm/kvm_host.h
> +++ b/arch/x86/include/asm/kvm_host.h
> @@ -697,6 +697,10 @@ struct kvm_x86_ops {
> void (*enable_nmi_window)(struct kvm_vcpu *vcpu);
> void (*enable_irq_window)(struct kvm_vcpu *vcpu);
> void (*update_cr8_intercept)(struct kvm_vcpu *vcpu, int tpr, int irr);
> + int (*has_virtual_interrupt_delivery)(struct kvm_vcpu *vcpu);
> + void (*update_apic_irq)(struct kvm_vcpu *vcpu, int max_irr);
> + void (*update_eoi_exitmap)(struct kvm_vcpu *vcpu, u32 vector, bool set);
> + void (*load_eoi_exitmap)(struct kvm_vcpu *vcpu);
> int (*set_tss_addr)(struct kvm *kvm, unsigned int addr);
> int (*get_tdp_level)(void);
> u64 (*get_mt_mask)(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio);
> @@ -991,6 +995,7 @@ int kvm_age_hva(struct kvm *kvm, unsigned long hva);
> int kvm_test_age_hva(struct kvm *kvm, unsigned long hva);
> void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
> int cpuid_maxphyaddr(struct kvm_vcpu *vcpu);
> +int kvm_cpu_has_injectable_intr(struct kvm_vcpu *v);
> int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu);
> int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu);
> int kvm_cpu_get_interrupt(struct kvm_vcpu *v);
> diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h
> index 21101b6..1003341 100644
> --- a/arch/x86/include/asm/vmx.h
> +++ b/arch/x86/include/asm/vmx.h
> @@ -62,6 +62,7 @@
> #define EXIT_REASON_MCE_DURING_VMENTRY 41
> #define EXIT_REASON_TPR_BELOW_THRESHOLD 43
> #define EXIT_REASON_APIC_ACCESS 44
> +#define EXIT_REASON_EOI_INDUCED 45
> #define EXIT_REASON_EPT_VIOLATION 48
> #define EXIT_REASON_EPT_MISCONFIG 49
> #define EXIT_REASON_WBINVD 54
> @@ -143,6 +144,7 @@
> #define SECONDARY_EXEC_WBINVD_EXITING 0x00000040
> #define SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080
> #define SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100
> +#define SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200
> #define SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400
> #define SECONDARY_EXEC_ENABLE_INVPCID 0x00001000
>
> @@ -180,6 +182,7 @@ enum vmcs_field {
> GUEST_GS_SELECTOR = 0x0000080a,
> GUEST_LDTR_SELECTOR = 0x0000080c,
> GUEST_TR_SELECTOR = 0x0000080e,
> + GUEST_INTR_STATUS = 0x00000810,
> HOST_ES_SELECTOR = 0x00000c00,
> HOST_CS_SELECTOR = 0x00000c02,
> HOST_SS_SELECTOR = 0x00000c04,
> @@ -207,6 +210,14 @@ enum vmcs_field {
> APIC_ACCESS_ADDR_HIGH = 0x00002015,
> EPT_POINTER = 0x0000201a,
> EPT_POINTER_HIGH = 0x0000201b,
> + EOI_EXIT_BITMAP0 = 0x0000201c,
> + EOI_EXIT_BITMAP0_HIGH = 0x0000201d,
> + EOI_EXIT_BITMAP1 = 0x0000201e,
> + EOI_EXIT_BITMAP1_HIGH = 0x0000201f,
> + EOI_EXIT_BITMAP2 = 0x00002020,
> + EOI_EXIT_BITMAP2_HIGH = 0x00002021,
> + EOI_EXIT_BITMAP3 = 0x00002022,
> + EOI_EXIT_BITMAP3_HIGH = 0x00002023,
> GUEST_PHYSICAL_ADDRESS = 0x00002400,
> GUEST_PHYSICAL_ADDRESS_HIGH = 0x00002401,
> VMCS_LINK_POINTER = 0x00002800,
> diff --git a/arch/x86/kvm/irq.c b/arch/x86/kvm/irq.c
> index ebd98d0..537ce4b 100644
> --- a/arch/x86/kvm/irq.c
> +++ b/arch/x86/kvm/irq.c
> @@ -38,37 +38,81 @@ int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
> EXPORT_SYMBOL(kvm_cpu_has_pending_timer);
>
> /*
> + * check if there is pending interrupt from
> + * non-APIC source without intack.
> + */
> +static int kvm_cpu_has_extint(struct kvm_vcpu *v)
> +{
> + if (kvm_apic_accept_pic_intr(v))
> + return pic_irqchip(v->kvm)->output; /* PIC */
> + else
> + return 0;
> +}
> +
> +/*
> + * check if there is injectable interrupt:
> + * when virtual interrupt delivery enabled,
> + * interrupt from apic will handled by hardware,
> + * we don't need to check it here.
> + */
> +int kvm_cpu_has_injectable_intr(struct kvm_vcpu *v)
> +{
> + if (!irqchip_in_kernel(v->kvm))
> + return v->arch.interrupt.pending;
> +
> + if (kvm_cpu_has_extint(v))
> + return 1;
> + else if (!kvm_apic_vid_enabled(v))
> + return kvm_apic_has_interrupt(v) != -1; /* LAPIC */
> +
I think:
if (kvm_cpu_has_extint(v))
return 1;
if(kvm_apic_vid_enabled(v))
return 0;
return kvm_apic_has_interrupt(v) != -1; /* LAPIC */
is clearer.
> + return 0;
> +}
> +
> +/*
> * check if there is pending interrupt without
> * intack.
> */
> int kvm_cpu_has_interrupt(struct kvm_vcpu *v)
> {
> - struct kvm_pic *s;
> -
> if (!irqchip_in_kernel(v->kvm))
> return v->arch.interrupt.pending;
>
> - if (kvm_apic_accept_pic_intr(v) && pic_irqchip(v->kvm)->output)
> - return pic_irqchip(v->kvm)->output; /* PIC */
> + if (kvm_cpu_has_extint(v))
> + return 1;
>
> return kvm_apic_has_interrupt(v) != -1; /* LAPIC */
> }
> EXPORT_SYMBOL_GPL(kvm_cpu_has_interrupt);
>
> /*
> + * Read pending interrupt(from non-APIC source)
> + * vector and intack.
> + */
> +static int kvm_cpu_get_extint(struct kvm_vcpu *v)
> +{
> + if (kvm_cpu_has_extint(v))
> + return kvm_pic_read_irq(v->kvm); /* PIC */
> + return -1;
> +}
> +
> +/*
> * Read pending interrupt vector and intack.
> */
> int kvm_cpu_get_interrupt(struct kvm_vcpu *v)
> {
> - struct kvm_pic *s;
> + int vector;
>
> if (!irqchip_in_kernel(v->kvm))
> return v->arch.interrupt.nr;
>
> - if (kvm_apic_accept_pic_intr(v) && pic_irqchip(v->kvm)->output)
> - return kvm_pic_read_irq(v->kvm); /* PIC */
> + vector = kvm_cpu_get_extint(v);
> +
> + if (kvm_apic_vid_enabled(v))
> + return vector; /* PIC */
> + else if (vector == -1)
> + vector = kvm_get_apic_interrupt(v); /* APIC */
>
No need "else" here:
if (kvm_apic_vid_enabled(v) || vector != -1)
return vector;
return kvm_get_apic_interrupt(v);
> - return kvm_get_apic_interrupt(v); /* APIC */
> + return vector;
> }
> EXPORT_SYMBOL_GPL(kvm_cpu_get_interrupt);
>
> diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
> index 0664c13..0dfbd47 100644
> --- a/arch/x86/kvm/lapic.c
> +++ b/arch/x86/kvm/lapic.c
> @@ -236,12 +236,14 @@ static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id)
> {
> apic_set_reg(apic, APIC_ID, id << 24);
> recalculate_apic_map(apic->vcpu->kvm);
> + ioapic_update_eoi_exitmap(apic->vcpu->kvm);
> }
>
> static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
> {
> apic_set_reg(apic, APIC_LDR, id);
> recalculate_apic_map(apic->vcpu->kvm);
> + ioapic_update_eoi_exitmap(apic->vcpu->kvm);
> }
>
> static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
> @@ -577,6 +579,63 @@ int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
> return result;
> }
>
> +static void kvm_apic_update_eoi_exitmap(struct kvm_vcpu *vcpu,
> + u32 vector, bool set)
> +{
> + kvm_x86_ops->update_eoi_exitmap(vcpu, vector, set);
> +}
> +
> +void kvm_update_eoi_exitmap(struct kvm *kvm, struct kvm_lapic_irq *irq)
> +{
We probably should move the whole function into vmx code, not just
bitmap update logic. Sorry for not mentioning it earlier.
> + struct kvm_vcpu *vcpu;
> + struct kvm_lapic **dst;
> + struct kvm_apic_map *map;
> + unsigned long bitmap = 1;
> + bool set;
> + int i;
> + DECLARE_BITMAP(vcpu_map, KVM_MAX_VCPUS);
> +
> + bitmap_zero(vcpu_map, 255);
> +
> + rcu_read_lock();
> + map = rcu_dereference(kvm->arch.apic_map);
> +
> + if (unlikely(!map)) {
> + bitmap_fill(vcpu_map, 255);
> + goto out;
> + }
> +
> + if (irq->dest_mode == 0) { /* physical mode */
> + if (irq->delivery_mode == APIC_DM_LOWEST ||
> + irq->dest_id == 0xff) {
> + bitmap_fill(vcpu_map, 255);
> + goto out;
> + }
> + dst = &map->phys_map[irq->dest_id & 0xff];
> + } else {
> + u32 mda = irq->dest_id << (32 - map->ldr_bits);
> +
> + dst = map->logical_map[apic_cluster_id(map, mda)];
> +
> + bitmap = apic_logical_id(map, mda);
> + }
> +
> + for_each_set_bit(i, &bitmap, 16) {
> + if (!dst[i])
> + continue;
> + set_bit(dst[i]->vcpu->vcpu_id, vcpu_map);
> + }
> +
> +out:
> + rcu_read_unlock();
> + kvm_for_each_vcpu(i, vcpu, kvm) {
> + if (!kvm_apic_present(vcpu))
> + continue;
> + set = test_bit(vcpu->vcpu_id, vcpu_map);
> + kvm_apic_update_eoi_exitmap(vcpu, irq->vector, set);
> + }
> +
> +}
> bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
> struct kvm_lapic_irq *irq, int *r)
> {
> @@ -740,6 +799,19 @@ int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
> return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
> }
>
> +static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
> +{
> + if (!(kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI) &&
> + kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) {
> + int trigger_mode;
> + if (apic_test_vector(vector, apic->regs + APIC_TMR))
> + trigger_mode = IOAPIC_LEVEL_TRIG;
> + else
> + trigger_mode = IOAPIC_EDGE_TRIG;
> + kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
> + }
> +}
> +
> static int apic_set_eoi(struct kvm_lapic *apic)
> {
> int vector = apic_find_highest_isr(apic);
> @@ -756,19 +828,26 @@ static int apic_set_eoi(struct kvm_lapic *apic)
> apic_clear_isr(vector, apic);
> apic_update_ppr(apic);
>
> - if (!(kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI) &&
> - kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) {
> - int trigger_mode;
> - if (apic_test_vector(vector, apic->regs + APIC_TMR))
> - trigger_mode = IOAPIC_LEVEL_TRIG;
> - else
> - trigger_mode = IOAPIC_EDGE_TRIG;
> - kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
> - }
> + kvm_ioapic_send_eoi(apic, vector);
> kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
> return vector;
> }
>
> +/*
> + * this interface assumes a trap-like exit, which has already finished
> + * desired side effect including vISR and vPPR update.
> + */
> +void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
> +{
> + struct kvm_lapic *apic = vcpu->arch.apic;
> +
> + trace_kvm_eoi(apic, vector);
> +
> + kvm_ioapic_send_eoi(apic, vector);
> + kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
> +}
> +EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
> +
> static void apic_send_ipi(struct kvm_lapic *apic)
> {
> u32 icr_low = kvm_apic_get_reg(apic, APIC_ICR);
> @@ -1071,6 +1150,7 @@ static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
> if (!apic_x2apic_mode(apic)) {
> apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
> recalculate_apic_map(apic->vcpu->kvm);
> + ioapic_update_eoi_exitmap(apic->vcpu->kvm);
> } else
> ret = 1;
> break;
> @@ -1318,6 +1398,7 @@ void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
> else
> static_key_slow_inc(&apic_hw_disabled.key);
> recalculate_apic_map(vcpu->kvm);
> + ioapic_update_eoi_exitmap(apic->vcpu->kvm);
> }
>
> if (!kvm_vcpu_is_bsp(apic->vcpu))
> diff --git a/arch/x86/kvm/lapic.h b/arch/x86/kvm/lapic.h
> index 9a8ee22..cf16ecb 100644
> --- a/arch/x86/kvm/lapic.h
> +++ b/arch/x86/kvm/lapic.h
> @@ -39,6 +39,7 @@ void kvm_free_lapic(struct kvm_vcpu *vcpu);
> int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu);
> int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu);
> int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu);
> +int kvm_apic_get_highest_irr(struct kvm_vcpu *vcpu);
> void kvm_lapic_reset(struct kvm_vcpu *vcpu);
> u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu);
> void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8);
> @@ -55,6 +56,8 @@ int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type);
> bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
> struct kvm_lapic_irq *irq, int *r);
>
> +void kvm_update_eoi_exitmap(struct kvm *kvm, struct kvm_lapic_irq *irq);
> +
> u64 kvm_get_apic_base(struct kvm_vcpu *vcpu);
> void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data);
> void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
> @@ -65,6 +68,7 @@ u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu);
> void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data);
>
> void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset);
> +void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector);
>
> void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr);
> void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu);
> @@ -126,4 +130,9 @@ static inline int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
> return kvm_apic_present(vcpu) && kvm_apic_sw_enabled(vcpu->arch.apic);
> }
>
> +static inline bool kvm_apic_vid_enabled(struct kvm_vcpu *vcpu)
> +{
> + return kvm_x86_ops->has_virtual_interrupt_delivery(vcpu);
> +}
> +
> #endif
> diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
> index dcb7952..b501d5a 100644
> --- a/arch/x86/kvm/svm.c
> +++ b/arch/x86/kvm/svm.c
> @@ -3573,6 +3573,27 @@ static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
> set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
> }
>
> +static int svm_has_virtual_interrupt_delivery(struct kvm_vcpu *vcpu)
> +{
> + return 0;
> +}
> +
> +static void svm_update_apic_irq(struct kvm_vcpu *vcpu, int max_irr)
> +{
> + return ;
> +}
You do not need this function any more since caller checks for NULL
pointer.
> +
> +static void svm_update_eoi_exitmap(struct kvm_vcpu *vcpu,
> + u32 vector, bool set)
> +{
> + return ;
> +}
> +
> +static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu)
> +{
> + return ;
> +}
> +
> static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
> {
> struct vcpu_svm *svm = to_svm(vcpu);
> @@ -4292,6 +4313,10 @@ static struct kvm_x86_ops svm_x86_ops = {
> .enable_nmi_window = enable_nmi_window,
> .enable_irq_window = enable_irq_window,
> .update_cr8_intercept = update_cr8_intercept,
> + .has_virtual_interrupt_delivery = svm_has_virtual_interrupt_delivery,
> + .update_apic_irq = svm_update_apic_irq;
Should not be set.
> + .update_eoi_exitmap = svm_update_eoi_exitmap;
> + .load_eoi_exitmap = svm_load_eoi_exitmap,
>
> .set_tss_addr = svm_set_tss_addr,
> .get_tdp_level = get_npt_level,
> diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
> index 4838e4f..f0ed77c 100644
> --- a/arch/x86/kvm/vmx.c
> +++ b/arch/x86/kvm/vmx.c
> @@ -432,6 +432,8 @@ struct vcpu_vmx {
>
> bool rdtscp_enabled;
>
> + unsigned long eoi_exit_bitmap[4];
> +
> /* Support for a guest hypervisor (nested VMX) */
> struct nested_vmx nested;
> };
> @@ -770,6 +772,12 @@ static inline bool cpu_has_vmx_apic_register_virt(void)
> SECONDARY_EXEC_APIC_REGISTER_VIRT;
> }
>
> +static inline bool cpu_has_vmx_virtual_intr_delivery(void)
> +{
> + return vmcs_config.cpu_based_2nd_exec_ctrl &
> + SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
> +}
> +
> static inline bool cpu_has_vmx_flexpriority(void)
> {
> return cpu_has_vmx_tpr_shadow() &&
> @@ -2508,7 +2516,8 @@ static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
> SECONDARY_EXEC_PAUSE_LOOP_EXITING |
> SECONDARY_EXEC_RDTSCP |
> SECONDARY_EXEC_ENABLE_INVPCID |
> - SECONDARY_EXEC_APIC_REGISTER_VIRT;
> + SECONDARY_EXEC_APIC_REGISTER_VIRT |
> + SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
> if (adjust_vmx_controls(min2, opt2,
> MSR_IA32_VMX_PROCBASED_CTLS2,
> &_cpu_based_2nd_exec_control) < 0)
> @@ -2522,7 +2531,8 @@ static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
>
> if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
> _cpu_based_2nd_exec_control &= ~(
> - SECONDARY_EXEC_APIC_REGISTER_VIRT);
> + SECONDARY_EXEC_APIC_REGISTER_VIRT |
> + SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
>
> if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
> /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
> @@ -2721,9 +2731,15 @@ static __init int hardware_setup(void)
> if (!cpu_has_vmx_ple())
> ple_gap = 0;
>
> - if (!cpu_has_vmx_apic_register_virt())
> + if (!cpu_has_vmx_apic_register_virt() ||
> + !cpu_has_vmx_virtual_intr_delivery())
> enable_apicv_reg_vid = 0;
>
> + if (enable_apicv_reg_vid)
> + kvm_x86_ops->update_cr8_intercept = NULL;
> + else
> + kvm_x86_ops->update_apic_irq = NULL;
> +
> if (nested)
> nested_vmx_setup_ctls_msrs();
>
> @@ -3838,7 +3854,8 @@ static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
> if (!ple_gap)
> exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
> if (!enable_apicv_reg_vid)
> - exec_control &= ~SECONDARY_EXEC_APIC_REGISTER_VIRT;
> + exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
> + SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
> return exec_control;
> }
>
> @@ -3883,6 +3900,15 @@ static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
> vmx_secondary_exec_control(vmx));
> }
>
> + if (enable_apicv_reg_vid) {
> + vmcs_write64(EOI_EXIT_BITMAP0, 0);
> + vmcs_write64(EOI_EXIT_BITMAP1, 0);
> + vmcs_write64(EOI_EXIT_BITMAP2, 0);
> + vmcs_write64(EOI_EXIT_BITMAP3, 0);
> +
> + vmcs_write16(GUEST_INTR_STATUS, 0);
> + }
> +
> if (ple_gap) {
> vmcs_write32(PLE_GAP, ple_gap);
> vmcs_write32(PLE_WINDOW, ple_window);
> @@ -4806,6 +4832,16 @@ static int handle_apic_access(struct kvm_vcpu *vcpu)
> return emulate_instruction(vcpu, 0) == EMULATE_DONE;
> }
>
> +static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
> +{
> + unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
> + int vector = exit_qualification & 0xff;
> +
> + /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
> + kvm_apic_set_eoi_accelerated(vcpu, vector);
> + return 1;
> +}
> +
> static int handle_apic_write(struct kvm_vcpu *vcpu)
> {
> unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
> @@ -5756,6 +5792,7 @@ static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
> [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
> [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
> [EXIT_REASON_APIC_WRITE] = handle_apic_write,
> + [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
> [EXIT_REASON_WBINVD] = handle_wbinvd,
> [EXIT_REASON_XSETBV] = handle_xsetbv,
> [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
> @@ -6105,6 +6142,63 @@ static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
> vmcs_write32(TPR_THRESHOLD, irr);
> }
>
> +static int vmx_has_virtual_interrupt_delivery(struct kvm_vcpu *vcpu)
> +{
> + return enable_apicv_reg_vid;
> +}
> +
> +static void vmx_update_rvi(int vector)
> +{
> + u16 status;
> + u8 old;
> +
> + status = vmcs_read16(GUEST_INTR_STATUS);
> + old = (u8)status & 0xff;
> + if ((u8)vector != old) {
> + status &= ~0xff;
> + status |= (u8)vector;
> + vmcs_write16(GUEST_INTR_STATUS, status);
> + }
> +}
> +
> +static void vmx_update_apic_irq(struct kvm_vcpu *vcpu, int max_irr)
> +{
> + if (!enable_apicv_reg_vid || max_irr == -1)
No need to check enable_apicv_reg_vid since the function will not be
called if vid is disabled.
> + return ;
> +
> + vmx_update_rvi(max_irr);
> +}
> +
> +static void vmx_update_eoi_exitmap(struct kvm_vcpu *vcpu,
> + u32 vector, bool set)
> +{
> + struct vcpu_vmx *vmx = to_vmx(vcpu);
> +
> + if (!enable_apicv_reg_vid)
> + return ;
> +
> + if (WARN_ONCE((vector > 255),
> + "KVM VMX: vector (%d) out of range\n", vector))
> + return;
> +
> + if (set)
> + set_bit(vector, vmx->eoi_exit_bitmap);
> + else
> + clear_bit(vector, vmx->eoi_exit_bitmap);
> +
> + kvm_make_request(KVM_REQ_EOIBITMAP, vcpu);
> +}
> +
> +static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu)
> +{
> + struct vcpu_vmx *vmx = to_vmx(vcpu);
> +
> + vmcs_write64(EOI_EXIT_BITMAP0, vmx->eoi_exit_bitmap[0]);
> + vmcs_write64(EOI_EXIT_BITMAP1, vmx->eoi_exit_bitmap[1]);
> + vmcs_write64(EOI_EXIT_BITMAP2, vmx->eoi_exit_bitmap[2]);
> + vmcs_write64(EOI_EXIT_BITMAP3, vmx->eoi_exit_bitmap[3]);
> +}
> +
> static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
> {
> u32 exit_intr_info;
> @@ -7365,6 +7459,10 @@ static struct kvm_x86_ops vmx_x86_ops = {
> .enable_nmi_window = enable_nmi_window,
> .enable_irq_window = enable_irq_window,
> .update_cr8_intercept = update_cr8_intercept,
> + .has_virtual_interrupt_delivery = vmx_has_virtual_interrupt_delivery,
> + .update_apic_irq = vmx_update_apic_irq,
> + .update_eoi_exitmap = vmx_update_eoi_exitmap,
> + .load_eoi_exitmap = vmx_load_eoi_exitmap,
>
> .set_tss_addr = vmx_set_tss_addr,
> .get_tdp_level = get_ept_level,
> diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
> index 3bdaf29..da3c6d6 100644
> --- a/arch/x86/kvm/x86.c
> +++ b/arch/x86/kvm/x86.c
> @@ -5534,7 +5534,7 @@ static void inject_pending_event(struct kvm_vcpu *vcpu)
> vcpu->arch.nmi_injected = true;
> kvm_x86_ops->set_nmi(vcpu);
> }
> - } else if (kvm_cpu_has_interrupt(vcpu)) {
> + } else if (kvm_cpu_has_injectable_intr(vcpu)) {
> if (kvm_x86_ops->interrupt_allowed(vcpu)) {
> kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
> false);
> @@ -5655,6 +5655,8 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
> kvm_handle_pmu_event(vcpu);
> if (kvm_check_request(KVM_REQ_PMI, vcpu))
> kvm_deliver_pmi(vcpu);
> + if (kvm_check_request(KVM_REQ_EOIBITMAP, vcpu))
> + kvm_x86_ops->load_eoi_exitmap(vcpu);
> }
>
> if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
> @@ -5663,10 +5665,15 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
> /* enable NMI/IRQ window open exits if needed */
> if (vcpu->arch.nmi_pending)
> kvm_x86_ops->enable_nmi_window(vcpu);
> - else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
> + else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
> kvm_x86_ops->enable_irq_window(vcpu);
>
> if (kvm_lapic_enabled(vcpu)) {
> + /* update archtecture specific hints for APIC
> + * virtual interrupt delivery */
> + if (kvm_x86_ops->update_apic_irq)
> + kvm_x86_ops->update_apic_irq(vcpu,
> + kvm_lapic_find_highest_irr(vcpu));
> update_cr8_intercept(vcpu);
> kvm_lapic_sync_to_vapic(vcpu);
> }
> diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h
> index 8e5c7b6..8ba5057 100644
> --- a/include/linux/kvm_host.h
> +++ b/include/linux/kvm_host.h
> @@ -133,6 +133,7 @@ static inline bool is_error_page(struct page *page)
> #define KVM_REQ_WATCHDOG 18
> #define KVM_REQ_MASTERCLOCK_UPDATE 19
> #define KVM_REQ_MCLOCK_INPROGRESS 20
> +#define KVM_REQ_EOIBITMAP 21
>
> #define KVM_USERSPACE_IRQ_SOURCE_ID 0
> #define KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID 1
> @@ -695,6 +696,7 @@ void kvm_get_intr_delivery_bitmask(struct kvm_ioapic *ioapic,
> int kvm_set_irq(struct kvm *kvm, int irq_source_id, u32 irq, int level);
> int kvm_set_msi(struct kvm_kernel_irq_routing_entry *irq_entry, struct kvm *kvm,
> int irq_source_id, int level);
> +bool kvm_irq_has_notifier(struct kvm *kvm, unsigned irqchip, unsigned pin);
> void kvm_notify_acked_irq(struct kvm *kvm, unsigned irqchip, unsigned pin);
> void kvm_register_irq_ack_notifier(struct kvm *kvm,
> struct kvm_irq_ack_notifier *kian);
> diff --git a/virt/kvm/ioapic.c b/virt/kvm/ioapic.c
> index cfb7e4d..7c8d9e0 100644
> --- a/virt/kvm/ioapic.c
> +++ b/virt/kvm/ioapic.c
> @@ -115,6 +115,37 @@ static void update_handled_vectors(struct kvm_ioapic *ioapic)
> smp_wmb();
> }
>
> +static void ioapic_update_eoi_exitmap_one(struct kvm_ioapic *ioapic, int pin)
> +{
> + union kvm_ioapic_redirect_entry *e;
> +
> + e = &ioapic->redirtbl[pin];
> +
> + if ((e->fields.trig_mode == IOAPIC_LEVEL_TRIG ||
> + kvm_irq_has_notifier(ioapic->kvm, KVM_IRQCHIP_IOAPIC, pin))) {
> + struct kvm_lapic_irq irqe;
> +
> + irqe.dest_id = e->fields.dest_id;
> + irqe.vector = e->fields.vector;
> + irqe.dest_mode = e->fields.dest_mode;
> + irqe.delivery_mode = e->fields.delivery_mode << 8;
> + kvm_update_eoi_exitmap(ioapic->kvm, &irqe);
> + }
> +}
> +
There is a bugs in exitbitmap recalculation that I've missed.
We need to zero all the exit bitmaps for all vcpus before we are
starting to recalculate them to get rid of stale bits.
> +void ioapic_update_eoi_exitmap(struct kvm *kvm)
> +{
> + struct kvm_ioapic *ioapic = kvm->arch.vioapic;
> + union kvm_ioapic_redirect_entry *e;
> + int index;
> +
> + for (index = 0; index < IOAPIC_NUM_PINS; index++) {
> + e = &ioapic->redirtbl[index];
> + if (!e->fields.mask)
> + ioapic_update_eoi_exitmap_one(ioapic, index);
> + }
> +}
> +
> static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
> {
> unsigned index;
> @@ -156,6 +187,8 @@ static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
> if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG
> && ioapic->irr & (1 << index))
> ioapic_service(ioapic, index);
> + if (!e->fields.mask)
> + ioapic_update_eoi_exitmap_one(ioapic, index);
> break;
> }
> }
> diff --git a/virt/kvm/ioapic.h b/virt/kvm/ioapic.h
> index a30abfe..e8d67cf 100644
> --- a/virt/kvm/ioapic.h
> +++ b/virt/kvm/ioapic.h
> @@ -82,5 +82,6 @@ int kvm_irq_delivery_to_apic(struct kvm *kvm, struct kvm_lapic *src,
> struct kvm_lapic_irq *irq);
> int kvm_get_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state);
> int kvm_set_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state);
> +void ioapic_update_eoi_exitmap(struct kvm *kvm);
>
> #endif
> diff --git a/virt/kvm/irq_comm.c b/virt/kvm/irq_comm.c
> index 2eb58af..0ac691f 100644
> --- a/virt/kvm/irq_comm.c
> +++ b/virt/kvm/irq_comm.c
> @@ -178,6 +178,24 @@ int kvm_set_irq(struct kvm *kvm, int irq_source_id, u32 irq, int level)
> return ret;
> }
>
> +bool kvm_irq_has_notifier(struct kvm *kvm, unsigned irqchip, unsigned pin)
> +{
> + struct kvm_irq_ack_notifier *kian;
> + struct hlist_node *n;
> + int gsi;
> +
> + rcu_read_lock();
> + gsi = rcu_dereference(kvm->irq_routing)->chip[irqchip][pin];
> + if (gsi != -1)
> + hlist_for_each_entry_rcu(kian, n, &kvm->irq_ack_notifier_list,
> + link)
> + if (kian->gsi == gsi)
> + return true;
> + rcu_read_unlock();
> +
> + return false;
> +}
> +
> void kvm_notify_acked_irq(struct kvm *kvm, unsigned irqchip, unsigned pin)
> {
> struct kvm_irq_ack_notifier *kian;
> @@ -202,6 +220,7 @@ void kvm_register_irq_ack_notifier(struct kvm *kvm,
> mutex_lock(&kvm->irq_lock);
> hlist_add_head_rcu(&kian->link, &kvm->irq_ack_notifier_list);
> mutex_unlock(&kvm->irq_lock);
> + ioapic_update_eoi_exitmap(kvm);
> }
>
> void kvm_unregister_irq_ack_notifier(struct kvm *kvm,
> @@ -211,6 +230,7 @@ void kvm_unregister_irq_ack_notifier(struct kvm *kvm,
> hlist_del_init_rcu(&kian->link);
> mutex_unlock(&kvm->irq_lock);
> synchronize_rcu();
> + ioapic_update_eoi_exitmap(kvm);
> }
>
> int kvm_request_irq_source_id(struct kvm *kvm)
> --
> 1.7.1
--
Gleb.
^ permalink raw reply [flat|nested] 7+ messages in thread
* RE: [PATCH v6 2/3] x86, apicv: add virtual interrupt delivery support
2012-12-12 10:54 ` Gleb Natapov
@ 2012-12-13 1:09 ` Zhang, Yang Z
2012-12-13 6:50 ` Gleb Natapov
0 siblings, 1 reply; 7+ messages in thread
From: Zhang, Yang Z @ 2012-12-13 1:09 UTC (permalink / raw)
To: Gleb Natapov
Cc: kvm@vger.kernel.org, mtosatti@redhat.com, Shan, Haitao,
Tian, Kevin
Gleb Natapov wrote on 2012-12-12:
> On Wed, Dec 12, 2012 at 12:56:47PM +0800, Yang Zhang wrote:
>> From: Yang Zhang <yang.z.zhang@Intel.com>
>>
>> Virtual interrupt delivery avoids KVM to inject vAPIC interrupts
>> manually, which is fully taken care of by the hardware. This needs
>> some special awareness into existing interrupr injection path:
>>
>> - for pending interrupt, instead of direct injection, we may need
>> update architecture specific indicators before resuming to guest.
>> - A pending interrupt, which is masked by ISR, should be also
>> considered in above update action, since hardware will decide
>> when to inject it at right time. Current has_interrupt and
>> get_interrupt only returns a valid vector from injection p.o.v.
>> Signed-off-by: Kevin Tian <kevin.tian@intel.com>
>> Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>
>> ---
>> diff --git a/arch/x86/kvm/irq.c b/arch/x86/kvm/irq.c
>> index ebd98d0..537ce4b 100644
>> --- a/arch/x86/kvm/irq.c
>> +++ b/arch/x86/kvm/irq.c
>> @@ -38,37 +38,81 @@ int kvm_cpu_has_pending_timer(struct kvm_vcpu
> *vcpu)
>> EXPORT_SYMBOL(kvm_cpu_has_pending_timer);
>>
>> /*
>> + * check if there is pending interrupt from
>> + * non-APIC source without intack.
>> + */
>> +static int kvm_cpu_has_extint(struct kvm_vcpu *v)
>> +{
>> + if (kvm_apic_accept_pic_intr(v))
>> + return pic_irqchip(v->kvm)->output; /* PIC */
>> + else
>> + return 0;
>> +}
>> +
>> +/*
>> + * check if there is injectable interrupt:
>> + * when virtual interrupt delivery enabled,
>> + * interrupt from apic will handled by hardware,
>> + * we don't need to check it here.
>> + */
>> +int kvm_cpu_has_injectable_intr(struct kvm_vcpu *v)
>> +{
>> + if (!irqchip_in_kernel(v->kvm))
>> + return v->arch.interrupt.pending;
>> +
>> + if (kvm_cpu_has_extint(v))
>> + return 1;
>> + else if (!kvm_apic_vid_enabled(v))
>> + return kvm_apic_has_interrupt(v) != -1; /* LAPIC */
>> +
> I think:
> if (kvm_cpu_has_extint(v))
> return 1;
> if(kvm_apic_vid_enabled(v)) return 0; return
> kvm_apic_has_interrupt(v) != -1; /* LAPIC */
> is clearer.
OK.
>> +/*
>> * Read pending interrupt vector and intack.
>> */
>> int kvm_cpu_get_interrupt(struct kvm_vcpu *v)
>> {
>> - struct kvm_pic *s;
>> + int vector;
>>
>> if (!irqchip_in_kernel(v->kvm))
>> return v->arch.interrupt.nr;
>> - if (kvm_apic_accept_pic_intr(v) && pic_irqchip(v->kvm)->output)
>> - return kvm_pic_read_irq(v->kvm); /* PIC */
>> + vector = kvm_cpu_get_extint(v);
>> +
>> + if (kvm_apic_vid_enabled(v))
>> + return vector; /* PIC */
>> + else if (vector == -1)
>> + vector = kvm_get_apic_interrupt(v); /* APIC */
>>
> No need "else" here:
> if (kvm_apic_vid_enabled(v) || vector != -1)
> return vector;
> return kvm_get_apic_interrupt(v);
Ok.
>> - return kvm_get_apic_interrupt(v); /* APIC */
>> + return vector;
>> }
>> EXPORT_SYMBOL_GPL(kvm_cpu_get_interrupt);
>> diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
>> index 0664c13..0dfbd47 100644
>> --- a/arch/x86/kvm/lapic.c
>> +++ b/arch/x86/kvm/lapic.c
>> @@ -236,12 +236,14 @@ static inline void kvm_apic_set_id(struct kvm_lapic
> *apic, u8 id)
>> { apic_set_reg(apic, APIC_ID, id << 24);
>> recalculate_apic_map(apic->vcpu->kvm);
>> + ioapic_update_eoi_exitmap(apic->vcpu->kvm); }
>>
>> static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id) {
>> apic_set_reg(apic, APIC_LDR, id);
>> recalculate_apic_map(apic->vcpu->kvm);
>> + ioapic_update_eoi_exitmap(apic->vcpu->kvm); }
>>
>> static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
>> @@ -577,6 +579,63 @@ int kvm_apic_match_dest(struct kvm_vcpu *vcpu,
> struct kvm_lapic *source,
>> return result;
>> }
>> +static void kvm_apic_update_eoi_exitmap(struct kvm_vcpu *vcpu,
>> + u32 vector, bool set)
>> +{
>> + kvm_x86_ops->update_eoi_exitmap(vcpu, vector, set);
>> +}
>> +
>> +void kvm_update_eoi_exitmap(struct kvm *kvm, struct kvm_lapic_irq *irq)
>> +{
> We probably should move the whole function into vmx code, not just
> bitmap update logic. Sorry for not mentioning it earlier.
Sure.
>> diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
>> index dcb7952..b501d5a 100644
>> --- a/arch/x86/kvm/svm.c
>> +++ b/arch/x86/kvm/svm.c
>> @@ -3573,6 +3573,27 @@ static void update_cr8_intercept(struct kvm_vcpu
> *vcpu, int tpr, int irr)
>> set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
>> }
>> +static int svm_has_virtual_interrupt_delivery(struct kvm_vcpu *vcpu)
>> +{
>> + return 0;
>> +}
>> +
>> +static void svm_update_apic_irq(struct kvm_vcpu *vcpu, int max_irr)
>> +{
>> + return ;
>> +}
> You do not need this function any more since caller checks for NULL
> pointer.
>> + .has_virtual_interrupt_delivery = svm_has_virtual_interrupt_delivery,
>> + .update_apic_irq = svm_update_apic_irq;
> Should not be set.
Sure.
>> + status = vmcs_read16(GUEST_INTR_STATUS);
>> + old = (u8)status & 0xff;
>> + if ((u8)vector != old) {
>> + status &= ~0xff;
>> + status |= (u8)vector;
>> + vmcs_write16(GUEST_INTR_STATUS, status);
>> + }
>> +}
>> +
>> +static void vmx_update_apic_irq(struct kvm_vcpu *vcpu, int max_irr)
>> +{
>> + if (!enable_apicv_reg_vid || max_irr == -1)
> No need to check enable_apicv_reg_vid since the function will not be
> called if vid is disabled.
Ok.
>> diff --git a/virt/kvm/ioapic.c b/virt/kvm/ioapic.c
>> index cfb7e4d..7c8d9e0 100644
>> --- a/virt/kvm/ioapic.c
>> +++ b/virt/kvm/ioapic.c
>> @@ -115,6 +115,37 @@ static void update_handled_vectors(struct kvm_ioapic
> *ioapic)
>> smp_wmb();
>> }
>> +static void ioapic_update_eoi_exitmap_one(struct kvm_ioapic *ioapic, int pin)
>> +{
>> + union kvm_ioapic_redirect_entry *e;
>> +
>> + e = &ioapic->redirtbl[pin];
>> +
>> + if ((e->fields.trig_mode == IOAPIC_LEVEL_TRIG ||
>> + kvm_irq_has_notifier(ioapic->kvm, KVM_IRQCHIP_IOAPIC, pin))) {
>> + struct kvm_lapic_irq irqe;
>> +
>> + irqe.dest_id = e->fields.dest_id;
>> + irqe.vector = e->fields.vector;
>> + irqe.dest_mode = e->fields.dest_mode;
>> + irqe.delivery_mode = e->fields.delivery_mode << 8;
>> + kvm_update_eoi_exitmap(ioapic->kvm, &irqe);
>> + }
>> +}
>> +
> There is a bugs in exitbitmap recalculation that I've missed.
> We need to zero all the exit bitmaps for all vcpus before we are
> starting to recalculate them to get rid of stale bits.
Right. I forget it too. So if consider to clear it, we should call ioapic_update_eoi_exitmap instead ioapic_update_eoi_exitmap_one when programming one program ioapic entry.
Best regards,
Yang
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v6 2/3] x86, apicv: add virtual interrupt delivery support
2012-12-13 1:09 ` Zhang, Yang Z
@ 2012-12-13 6:50 ` Gleb Natapov
0 siblings, 0 replies; 7+ messages in thread
From: Gleb Natapov @ 2012-12-13 6:50 UTC (permalink / raw)
To: Zhang, Yang Z
Cc: kvm@vger.kernel.org, mtosatti@redhat.com, Shan, Haitao,
Tian, Kevin
On Thu, Dec 13, 2012 at 01:09:11AM +0000, Zhang, Yang Z wrote:
> >> +static void ioapic_update_eoi_exitmap_one(struct kvm_ioapic *ioapic, int pin)
> >> +{
> >> + union kvm_ioapic_redirect_entry *e;
> >> +
> >> + e = &ioapic->redirtbl[pin];
> >> +
> >> + if ((e->fields.trig_mode == IOAPIC_LEVEL_TRIG ||
> >> + kvm_irq_has_notifier(ioapic->kvm, KVM_IRQCHIP_IOAPIC, pin))) {
> >> + struct kvm_lapic_irq irqe;
> >> +
> >> + irqe.dest_id = e->fields.dest_id;
> >> + irqe.vector = e->fields.vector;
> >> + irqe.dest_mode = e->fields.dest_mode;
> >> + irqe.delivery_mode = e->fields.delivery_mode << 8;
> >> + kvm_update_eoi_exitmap(ioapic->kvm, &irqe);
> >> + }
> >> +}
> >> +
> > There is a bugs in exitbitmap recalculation that I've missed.
> > We need to zero all the exit bitmaps for all vcpus before we are
> > starting to recalculate them to get rid of stale bits.
> Right. I forget it too. So if consider to clear it, we should call ioapic_update_eoi_exitmap instead ioapic_update_eoi_exitmap_one when programming one program ioapic entry.
>
Yes.
--
Gleb.
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2012-12-13 6:50 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2012-12-12 4:56 [PATCH v6 0/3] x86, apicv: Add APIC virtualization support Yang Zhang
2012-12-12 4:56 ` [PATCH v6 1/3] x86, apicv: add APICv register " Yang Zhang
2012-12-12 4:56 ` [PATCH v6 2/3] x86, apicv: add virtual interrupt delivery support Yang Zhang
2012-12-12 10:54 ` Gleb Natapov
2012-12-13 1:09 ` Zhang, Yang Z
2012-12-13 6:50 ` Gleb Natapov
2012-12-12 4:56 ` [PATCH v6 3/3] x86, apicv: add virtual x2apic support Yang Zhang
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